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Resilient neural network — Innatera Nanosystems B.V. (US20260017500A1)

Innatera Nanosystems B.V. · Google Patents

Google Patents · Patents · License: Open Access

patent, google patents, intellectual property, US20260017500A1, Innatera Nanosystems B.V., Sumeet Susheel Kumar, en, 2026

ABSTRACT

Abstract

The present invention discloses a spiking neural network for classifying input signals. The spiking neural network comprises a plurality of spiking neurons, and a plurality of synaptic elements interconnecting the spiking neurons to form the network. Each synaptic element is adapted to receive a synaptic input signal and apply a weight to the synaptic input signal to generate a synaptic output signal, the synaptic elements being configurable to adjust the weight applied by each synaptic element. Furthermore, each of the spiking neurons is adapted to receive one or more of the synaptic output signals from one or more of the synaptic elements, and generate a spatio-temporal spike train output signal in response to the received one or more synaptic output signals. The spiking neural network is partitioned into multiple sub-networks, wherein each sub-network comprises a sub-set of the spiking neurons connected to receive synaptic output signals from a sub-set of the synaptic elements. The sub-network is adapted to generate a sub-network output pattern signal in response to a sub-network input pattern signal applied to the sub-network. Furthermore, each sub-network forms part of one or multiple cores in an array of cores, each core consisting of a programmable network of spiking neurons implemented in hardware or a combination of hardware and software. Communication between cores in the core array is arranged through a programmable interconnect structure.

Description

TECHNICAL FIELD

This disclosure generally relates to automatic signal recognition techniques, and more particularly, to system and method for hardware-resilient deep-learning inference accelerators using spiking neurons.

BACKGROUND

Automatic signal recognition (ASR) refers to the recognition of signals through the identification of their constituent features. ASR is utilized in a range of applications, for example to recognize the voice of a speaker and spoken words in a voice/speech recognition system, to recognize arrhythmias in electrocardiograms (ECG), to determine the shape of a gesture in a motion-controlled system, among others. ASR is typically performed by characterizing patterns present in short samples of an input signal, and thus accurate pattern recognition capabilities are fundamental to an effective ASR system.

Measuring some physical quantities to derive input signals for an ASR system may require the fusion of data from multiple types of sensors. For example, recognizing a hand gesture using a hand-held input device may necessitate the fusion of data from an accelerometer, to measure motion, and data from a gyroscope, to measure orientation.

Combining data from both sensors enables the detection of gestures in three-dimensional space.

In general, data fusion refers to the integration of data gathered from disparate, and potentially heterogeneous sources, in order to decrease the uncertainty in interpretation of data from those individual sources. It is important that during the fusion process, essential features in the disparate input signals are adequately represented in the fused signal.

Pattern recognition and fusion are typically performed using microprocessors, and/or digital signal processors, both of which implement a stored program architecture. This architecture is inherently inefficient for analytics of streaming data. On a single processor, the extraction and recognition of patterns is carried out sequentially. This is because the pattern extraction and identification are realized in terms of the generic, simplistic instruction sets (e.g. RISC or CISC instruction sets), resulting in lengthy execution sequences for every pattern in the signal sample. Complex patterns in the input signal necessitate the use of more complex signal processing algorithms, which in a system requiring real-time responses from the pattern recognition engine, further necessitates the use of higher clock frequencies for the processor. In power-constrained devices (such as portable electronic devices, wearable devices, etc.), this is not feasible. Furthermore, due to the sequential execution paradigm, the latency and power dissipation of pattern recognition operations on a microprocessor increase greatly as the complexity and repertoire of patterns increases. The presence of noise in the input signals further increases the complexity of analysis, and adversely impacts performance and efficiency.

Data fusion is a non-native operation for microprocessors. This means that before input signals or data streams can be fused, their information content must be extracted, and thereafter combined with corresponding content from other streams. Consequently, in microprocessor implementations, each input signal/data source for fusion is processed separately by independent pattern recognition pipelines, followed by a rule-based framework to combine the disparate pattern recognition outcomes. This approach requires multiple invocations of the pattern recognition infrastructure, for each input signal or data stream, leading to increased power dissipation. Furthermore, the limitations of load-store architecture microprocessors and digital signal processors (DSPs) for pattern recognition mean that as pattern complexity increases, the power and latency costs of recognizing these patterns also increase. While the latency cost can be mitigated by increasing clock frequency, this is achieved at the cost of further increased power dissipation. Similarly, the quality of fusion is limited by the complexity of processing and ASR carried out on input signals, the number of signals being fused, and the computational capabilities of the microprocessor or DSP. The sequential nature of processing reduces the throughput of fusion-based ASR, thus, as complexity of patterns in signals increases, the number of input signals that can be fused using the microprocessor or DSP, decreases.

Artificial neural networks in the form of Deep neural networks (DNNs) have been proposed as an alternative to a microprocessor implementation. DNNs form the basis for large number of machine learning applications; starting with speech and image recognition, the number of applications that utilize DNNs has increased exponentially, but these suffer from intrinsic limitations, mainly for processing large amount of data or fast adaptation to a changing environment.

Initially, hardware deep network accelerators have been implemented on standard synchronous digital logic. The high level of parallelism of neural networks is not replicated in the (typically) serial and time-multiplexed processing in digital systems; conversely, computational primitives of hardware DNN emulator realized as analog computing nodes, where memory and processing elements are co-localized, offer significant improvements in terms of speed, size, and power consumption.

In biological neural network models each individual neuron communicate asynchronously and through sparse events, or spikes. In such event-based spiking neural network (SNN) only neurons who change the state generate spikes and may trigger signal processing in subsequent layers, consequently, saving computational resources. Spiking neural networks (SNN) are a promising means of realizing ASR for many different applications.

SNNs encode information in the form of one or more precisely timed (voltage) spikes, rather than as integer or real-valued vectors. Computations for inference (i.e. inferring the presence of a certain feature in an input signal) are effectively performed in the analog and temporal domains. For this reason, SNNs are typically realized in hardware as full-custom mixed signal integrated circuits. This enables them to perform inference functions with several orders of magnitude lower energy consumption than their artificial neural network counterparts, in addition to having smaller network sizes.

SNNs consist of a network of spiking neurons interconnected by synapses that dictate the strength of the connections between the spiking neurons. This strength is represented as a weight, which moderates the effect of the output of a pre-synaptic neuron on the input to a post-synaptic neuron. Typically, these weights are set in a training process that involves exposing the network to a large volume of labelled input data, and gradually adjusting the weights of the synapses until a desired network output is achieved.

SNNs can be directly applied to pattern recognition and sensor data fusion, relying on the principle that amplitude-domain, time-domain, and frequency domain features in an input signal can be encoded into unique spatial- and temporal-coded spike sequences.

The generation of these sequences relies on the use of one or more ensembles of spiking neurons, an ensemble being a co-operating group of neurons. Each ensemble performs a specific signal processing function, that is to say for example feature encoding, conditioning, filtering, data fusion, classification. Each ensemble consists of one or more interconnected layers of spiking neurons, with the connectivity within and between layers following a certain topology. The size of each ensemble (the number of neurons), their connectivity (topology and number of synapses), and their configuration (weights and number of layers) are dependent on the characteristics of the input signal, for example dynamic range, bandwidth, timescales or complexity of features in the input signal. Consequently, the ensembles used in the case of a voice pattern matching system are likely to differ from those used in a handwriting recognition system.

Commonly, as complexity increases of features to be recognized in an input signal, so does the size of ensembles required to process them. Spiking neural network hardware can utilize configurable arrays of spiking neurons, synapses, connected using a programmable interconnect structure that facilitates the implementation of any arbitrary connection topology. However, in order to implement a large ensemble, it is necessary that the underlying SNN hardware have at least as many neurons and synapses as required.

Although the elementary operations required by an SNN are very efficiently realized by analog electronic circuitry, the unavoidable variation in micro-electronic circuits due to the fabrication process induces distortions in their functional properties, for example resistance, capacitance, gain, time response et cetera. Especially at smaller fabrication process geometries, and lower operating currents, these circuits are increasingly susceptible to quantum effects and external noise, which effectively reduces signal-to-noise ratio and limits processing performance. The impact of these non-idealities is increased in the case of large arrays where the driver, biasing, encoder/decoder circuits are shared by a greater number of devices, over longer interconnects.

SUMMARY

To address the above discussed drawbacks of the prior art, there is proposed, according to a first aspect of the disclosure, a spiking neural network for classifying input signals. The spiking neural network comprising a plurality of spiking neurons, and a plurality of synaptic elements interconnecting the spiking neurons to form the network, wherein each synaptic element is adapted to receive a synaptic input signal and apply a weight to the synaptic input signal to generate a synaptic output signal, the synaptic elements being configurable to adjust the weight applied by each synaptic element. Each of the spiking neurons is adapted to receive one or more of the synaptic output signals from one or more of the synaptic elements, and generate a spatio-temporal spike train output signal in response to the received one or more synaptic output signals. The network is partitioned into multiple sub-networks, wherein each sub-network comprises a sub-set of the spiking neurons connected to receive synaptic output signals from a sub-set of the synaptic elements. The sub-network is adapted to generate a sub-network output pattern signal in response to a sub-network input pattern signal applied to the sub-network. Furthermore, each sub-network forms part of one or multiple cores in an array of cores, each core consisting of a programmable network of spiking neurons implemented in hardware or a combination of hardware and software, and communication between cores in the core array is arranged through a programmable interconnect structure.

In an embodiment, the programmable interconnect structure comprises a switchable matrix.

In an embodiment, the switchable matrix comprises a plurality of routers adapted to route a plurality of output signals from a first core in the core array to a plurality of inputs of a second core in the core array.

In an embodiment, the programmable interconnect structure forms a packet switching network between the cores in the core array. In an embodiment, the programmable interconnect structure uses an address-event representation. In an embodiment, the programmable interconnect structure uses synchronous or asynchronous communication. In an embodiment, the core array is implemented in an integrated circuit and the programmable interconnect structure comprises a network-on-a-chip.

In an embodiment, the network-on-chip is real-time configurable.

In an embodiment, either a learning rule, weight storage mechanism or communication protocol to the synaptic elements is heterogeneously applied in a single core of the core array. In an embodiment, either a learning rule, weight storage mechanism or communication protocol to the synaptic elements is heterogeneously applied over a plurality of the cores in the core array. In an embodiment, a learning rule configuration of one or more of the cores in the core array is implemented using a learning rule block. In an embodiment, the cores using the same learning rule use a common learning rule block which implements the learning rule.

In an embodiment, the distribution of learning rules within each core and/or over the cores in the core array is dynamically configurable at runtime.

In an embodiment, one of the sub-networks is a part of a classifier for classifying input signals of the sub-network.

In an embodiment, one of the sub-networks is a part of an ensemble of classifiers for classifying input signals to that sub-network. In an embodiment, the weights of the synaptic elements are configured using stochastic weight updates.

In an embodiment, the weights of the synaptic elements are bounded by bound values, wherein the bound values are stochastic values.

According to a second aspect of the disclosure, an integrated circuit is disclosed comprising the spiking neural network implemented in the core array of a first aspect of the disclosure.

According to a third aspect of the disclosure a method is disclosed of partitioning and mapping a spiking neural network onto a core array. Here, the spiking neural network comprises a plurality of spiking neurons, and a plurality of synaptic elements interconnecting the spiking neurons to form the network, wherein each synaptic element is adapted to receive a synaptic input signal and apply a weight to the synaptic input signal to generate a synaptic output signal, the synaptic elements being configurable to adjust the weight applied by each synaptic element, and wherein each of the spiking neurons is adapted to receive one or more of the synaptic output signals from one or more of the synaptic elements, and generate a spatio-temporal spike train output signal in response to the received one or more synaptic output signals. Furthermore, the core array comprises multiple cores, wherein each core consists of a programmable network of spiking neurons implemented in hardware or a combination of hardware and software and wherein the communication between cores in the core array is arranged through a programmable interconnect structure. Here, the method comprises that the network is partitioned into multiple sub-networks, wherein each sub-network comprises a sub-set of spiking neurons connected to receive synaptic output signals from a sub-set of the synaptic elements. The sub-network is adapted to generate a sub-network output pattern signal from the sub-set of spiking neurons, in response to sub-network input pattern signal applied to the sub-set of synaptic elements, wherein each sub-network

TECHNICAL FIELD

BACKGROUND

Combining data from both sensors enables the detection of gestures in three-dimensional space.

SUMMARY

In an embodiment, the programmable interconnect structure comprises a switchable matrix.

In an embodiment, the network-on-chip is real-time configurable.

In an embodiment, the distribution of learning rules within each core and/or over the cores in the core array is dynamically configurable at runtime.

In an embodiment, one of the sub-networks is a part of a classifier for classifying input signals of the sub-network.

In an embodiment, the weights of the synaptic elements are bounded by bound values, wherein the bound values are stochastic values.

According to a second aspect of the disclosure, an integrated circuit is disclosed comprising the spiking neural network implemented in the core array of a first aspect of the disclosure.

In an embodiment, the partitioning of the spiking neural network into the sub-networks implemented in the one or more cores is determined by a mapping methodology.

The mapping methodology comprises a constraint-driven partitioning. The constraint is a performance metric linked to the function of each respective sub-network.

According to a fourth aspect of the disclosure, a spiking neural network is disclosed. The spiking neural network comprises a plurality of spiking neurons implemented in hardware or a combination of hardware and software, and a plurality of synaptic elements interconnecting the spiking neurons to form the network, wherein each synaptic element is adapted to receive a synaptic input signal and apply a weight to the synaptic input signal to generate a synaptic output signal, the synaptic elements being configurable to adjust the weight applied by each synaptic element, and wherein each of the spiking neurons is adapted to receive one or more of the synaptic output signals from one or more of the synaptic elements, and generate a spatio-temporal spike train output signal in response to the received one or more synaptic output signals. Furthermore, a learning rule, weight storage mechanism and/or communication protocol is heterogeneously applied over the neurons and/or the synaptic elements in the spiking neural network.

According to a fifth aspect of the disclosure, a spiking neural network is disclosed comprising a spiking neuron, and a synaptic element connected to the spiking neuron. Here, the synaptic element comprises a first and second receptor adapted to receive a synaptic input signal, wherein the first and second receptor respectively generate a first and second receptor signal on the basis of the synaptic input signal. The synaptic element applies a weight to the first receptor signal to generate a synaptic output signal, the synaptic element being configurable to adjust the weight applied by the synaptic element at least on the basis of the second receptor signal. The spiking neuron is adapted to receive the synaptic output signal from the synaptic element, and generate a spatio-temporal spike train output signal at least in response to the received synaptic output signal.

In an embodiment, the neuron emits a control signal, wherein the control signal adjusts, together with the second receptor signal, the weight applied by the synaptic element.

In an embodiment, the control signal is a back-propagating signal.

In an embodiment, the neuron comprises a dendrite, axon and soma, wherein the control signal stems from the dendrite and/or axon and/or soma of the neuron.

In an embodiment, the control signal comprises one or more spikes generated by an action potential in the neuron. In an embodiment, the decay time of the first receptor is faster than the decay time of the second receptor. In an embodiment, the first receptor generates a sourcing or sinking current for the spiking neuron.

In an embodiment, the first receptor comprises a low-pass filter. In an embodiment, the second receptor forms a voltage-gated receptor. In an embodiment, the second receptor comprises a low-pass filter, band-pass filter, high-pass filter and/or amplifier. In an embodiment, the first receptor is an AMPA receptor, or a GABA receptor, or a NMDA receptor.

According to a sixth aspect of the disclosure, a method is disclosed for adjusting the weight of a synaptic element in a spiking neural network, the spiking neural network comprising a spiking neuron connected to the synaptic element. The synaptic element comprises a first and second receptor adapted to receive a synaptic input signal, wherein the first and second receptor receive the synaptic input signal and respectively generate a first and second receptor signal on the basis of the synaptic input signal. The synaptic element applies a weight to the first receptor signal to generate a synaptic output signal. On the basis of at least the second receptor signal the weight of the synaptic element is adjusted, and the spiking neuron receives the synaptic output signal from the synaptic element and generates a spatio-temporal spike train output signal at least in response to the received synaptic output signal.

In an embodiment, the neuron emits a control signal, wherein the control signal adjusts, together with the second receptor signal, the weight applied by the synaptic element.

In an embodiment, the control signal is a back-propagating signal.

In an embodiment, the neuron comprises a dendrite, axon and soma, wherein the control signal stems from the dendrite and/or axon and/or soma of the neuron.

According to a seventh aspect of the present disclosure, an integrated circuit is disclosed comprising the spiking neural network of the fifth aspect of the present disclosure.

According to an eight aspect of the present disclosure, a method is disclosed for configuring a spiking neural network to diminish noise effects in the spiking neural network. The spiking neural network comprises a plurality of spiking neurons implemented in hardware or a combination of hardware and software, and a plurality of synaptic elements interconnecting the spiking neurons to form the network. Each synaptic element is adapted to receive a synaptic input signal and apply a weight to the synaptic input signal to generate a synaptic output signal, the synaptic elements being configurable to adjust the weight applied by each synaptic element. Each of the spiking neurons is adapted to receive one or more of the synaptic output signals from one or more of the synaptic elements, and generate a spatio-temporal spike train output signal in response to the received one or more synaptic output signals. The synaptic drive Î i of one of the spiking neuron i in the spiking neural network is a time-dependent function describing a total transfer function of all synaptic elements that are connected into the neuron. The method comprises obtaining an expression for the variance of each of the synaptic drives Î i , the expression for the variance depending on a control parameter. The variance of each of the synaptic drives Î i is adjustable by adjusting the control parameter. The control parameter is adjusted such that the variance of each of the synaptic drives Î i lies below a predetermined value such that the synaptic drive Î i of each of the neuron i in the spiking neural network is bound around an equilibrium point Î i * of the synaptic drive Î i where noise effects are minimal.

In an embodiment, the synaptic drive Î i of the spiking neuron i in the spiking neural network can be written in vector form for all neurons in the spiking neural network as Î=(Î 1 , . . . , Î n ) T , with n the number of neurons in the spiking neural network, and wherein Î satisfies the formula:

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where N(Î(t)) is a nominal matrix part and Ï(T) is a state-dependent noise matrix for the Gaussian white noise process dÏ(t), where Ï is a Wiener process which describes noise in the spiking neural network, wherein the expression for dÎ is rewritable in terms of the variance-covariance matrix K(t) of Î(t) satisfying the following continuous-time algebraic Lyapunov equation:

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wherein the step of obtaining an expression for the variance of each of the synaptic drives Î i comprises determining the diagonal values of the variance-covariance matrix K(t).

In an embodiment, the equilibrium point Î i * of the synaptic drive Î i can be written in vector form for all neurons in the spiking neural network as Î*=(Î 1 *, . . . , Î n *) T , for which the noise matrix Ï is zero, i.e. Ï(Î*)=0.

In an embodiment, the control parameter is adjusted by means of a computer simulation.

According to a ninth aspect of the present disclosure, a spiking neural network is disclosed, comprising a plurality of spiking neurons implemented in hardware or a combination of hardware and software, and a plurality of synaptic elements interconnecting the spiking neurons to form the network. Each synaptic element is adapted to receive a synaptic input signal and apply a weight to the synaptic input signal to generate a synaptic output signal, the synaptic elements being configurable to adjust the weight applied by each synaptic element. Each of the spiking neurons is adapted to receive one or more of the synaptic output signals from one or more of the synaptic elements, and generate a spatio-temporal spike train output signal in response to the received one or more synaptic output signals. The synaptic drive Î i of one of the spiking neuron i in the spiking neural network is a time-dependent function describing a total transfer function of all synaptic elements that are connected into the neuron. The variance of each of the synaptic drives Î i lies below a predetermined value such that the synaptic drive Î i of each of the neuron i in the spiking neural network is bound around an equilibrium point Î i * of the synaptic drive Î i where noise effects are minimal.

BRIEF DESCRIPTION OF DRAWINGS

Embodiments will now be described, by way of example only, with reference to the accompanying schematic drawings in which corresponding reference symbols indicate corresponding parts, and in which:

FIG. 1 shows an exemplary neural network, consisting of neurons and synaptic elements;

FIG. 2 shows schematically a spiking neural network within a microcontroller integrated circuit;

FIG. 3 shows the high-level architecture for learning systems with an array of neuromorphic cores;

FIG. 4 shows a graphical representation of the boosting algorithm within a single core;

FIG. 5 shows a graphical representation of combining multiple ensemble systems within a single core;

FIG. 6 shows a graphical representation of combining multiple ensemble systems over multiple cores in a multicore implementation;

FIG. 7 A shows a conceptual diagram of a synaptic structure;

FIG. 7 B shows a conceptual diagram of a neuro-synaptic structure;

FIG. 8 shows a net activity of an unbounded network; and

FIG. 9 shows a net activity of a bounded network.

The figures are intended for illustrative purposes only, and do not serve as restriction of the scope or the protection as laid down by the claims.

DESCRIPTION OF EMBODIMENTS

Hereinafter, certain embodiments will be described in further detail. It should be appreciated, however, that these embodiments may not be construed as limiting the scope of protection for the present disclosure.

FIG. 1 is a simplified diagram of a neural network 100 . The neurons 1 are connected to each other via synaptic elements 2 . In order to not clutter the drawing, only a small number of neurons and synaptic elements are shown (and only some have a reference numeral attached to them). The connecting topology shown in FIG. 1 , i.e. the way in which the synaptic elements 2 connect the neurons 1 with each other, is merely an example and many other topologies may be employed. Each synaptic element 2 can transmit a signal to an input of a neuron 1 , and each neuron 1 that receives the signal can process the signal and can subsequently generate an output, which is transmitted via further synaptic elements 2 to other neurons 1 . Each synaptic element 2 has a certain weight assigned to it, which is applied to each synaptic input signal that the synaptic element receives and transmits, to produce a weighted synaptic output signal. The weight of a synaptic element is thus a measure of the kind of causal relationship between the two neurons 1 that are connected by the synaptic element 2 . The relationship can be causal (positive weight), anti-causal (negative weight) or non-existent (zero weight).

The neurons 1 and synaptic elements 2 can be implemented in hardware, for example using analog circuit elements or digital hardwired logic circuits. They can also be implemented partly in hardware and partly in software, or entirely in software. Implementation in hardware or least partly in hardware is preferred, i.e. a hardware circuit or element is used to perform the functions of the individual neurons, rather than using a large processor executing software where the software mimics individual neurons. These (part) hardware implementations achieve faster processing, e.g. enabling much faster pattern recognition, and event-driven processing in which blocks of neurons and synaptic elements are only activated when needed.

The neural network 100 can be a spiking neural network. The neurons 1 are then spiking neurons, which generate a neuron output signal in the form of one or more spikes or neuron generated events. The spiking neurons 1 may be configured to fire (i.e. generate an output spike) only when a membrane potential (e.g. an energy potential, or voltage or current level) within the neuron reaches a predetermined threshold value. The membrane potential of the spiking neuron changes as a result of the received input signals, i.e. the synaptic output signals received by the neuron from the synaptic elements are accumulated, integrated, or otherwise processed to alter the membrane potential. When a weight of a synaptic element 2 is positive, a synaptic output signal received from that synaptic element excites the spiking neurons 1 which receive the signal, raising their membrane potentials. When a weight of a synaptic element 2 is negative, a synaptic output signal received from that synaptic element inhibits the spiking neurons 1 which receive the signal, lowering their membrane potentials. When a weight of a synaptic element 2 is zero, a synaptic output signal received from that synaptic element does not have any effect on the spiking neurons 1 which receive the signal.

When the membrane potential of a spiking neuron 1 reaches the threshold value, the neuron fires, generating a spike at the time of firing, and the membrane potential is reduced as a result of the firing. If the membrane potential subsequently again reaches the threshold value, the neuron will fire again, generating a second spike. Each spiking neuron 1 is thus configured to generate one or more spikes in response to input signals received from the connected synaptic elements 2 , the spikes forming a spatio-temporal spike train. Since a spiking neuron 1 only fires when its membrane potential reaches the predetermined threshold value, the coding and processing of temporal information is incorporated into the neural network 100 . In this way, spatio-temporal spike trains are generated in the spiking neural network 100 , which are temporal sequences of spikes generated by the spiking neurons 1 of the network 100 .

The temporal characteristics of the spike trains encode amplitude and frequency features of the input signal. The temporal characteristics comprise: the latency between onset of stimulus (e.g. an input signal from a synaptic element) and generation of a spike at the output of a neuron; the latency between successive spikes from the same neuron; and the number of spikes fired by the neuron in the time duration for which the input stimulus is applied.

The synaptic elements 2 can be configurable such that for example the respective weights of the synaptic elements can be varied, for example by training the neural network 100 . The neurons 1 can be configurable in the way they respond to a signal from a synaptic element. For example, in the case of spiking neural networks, the neurons 1 can be configured in the way a certain signal increases or decreases the membrane potential, the time it takes for the membrane potential to naturally decay towards a resting potential, the value of the resting potential, the threshold value that triggers a spike of the spiking neuron 1 . The configuration of the neurons 1 can for example be kept constant during training, or be variable and set in a training of the neural network 100 on a particular training set.

Input signals 11 are for example multiple, disparate, sampled input signals, or spatio-temporal spike trains. The input can be an analog-to-digital converted value of a signal sample, or the digital value of the sample in the case of for example an analog or digital integrator, or the analog value of the sample in the case of an analog integrator.

Output signals 12 of the neural network 100 are for example spatio-temporal spike trains, which can be read out from the output neurons 1 and further classified and transformed by an output transformation stage into a set of digital values corresponding to the type of output code selected by the user.

FIG. 2 illustrates one embodiment of the high-level architecture of the microcontroller integrated circuit 100 comprising a spiking neural network 110 . In this context, microcontrollers 110 are economical means of data collection, sensing, pattern recognition and actuating the physical signals.

The spiking neural network 110 is connected to one or more streaming input data ports 111 , which provide the spiking neural network 110 with input which will be converted into spatio-temporal spike trains. The spiking neural network 110 is connected to one or more output ports 112 . A memory mapped control and configuration interface 113 controls the configuration parameters of the spiking neural network 110 , for example the synaptic weights and/or the neuron configuration and further can include peripherals (e.g. A/D converters, D/A converters, bandgaps, PLLs) and circuits for control and adaptation of neuron, synapse and plasticity (learning) circuits, among others. The interface 113 reads out a memory device 102 where the settings for the spiking neural network 110 are saved and sends signals to the spiking neural network 110 to set the hardware accordingly. The interface 113 could send analog signals to the spiking neural network 110 . The settings could include configuration parameters of each neuron 1 or synaptic element 2 of the spiking neural network 110 , or the network topology.

Each neuron 1 can have a set of configuration parameters that control the precise firing behaviour of that neuron 1 . For example, the neuron may be designed with a firing threshold, which represents a threshold of a voltage, energy, or other variable which accumulates in the neuron as a result of receiving inputs, and where the neuron generates an output spike (such as a voltage, current or energy spike) when the accumulated variable meets or exceeds the firing threshold. The neuron may implement an integration function which integrates the inputs to the neuron to determine the adjustment to the accumulated variable. In addition, the neuron may also be designed with: (a) a leakage rate, which represents the rate at which the accumulated variable in the neuron decays over time; (b) a resting value of the accumulated variable, which represents the value to which the accumulated variable will decay over time in the absence of any input signals to the neuron; (c) an integration time constant, which represents the time over which an input signal is integrated to determine any increase in the accumulated variable in the neuron; (d) a refractory level, which represents the value of the accumulated variable in the neuron immediately after firing of the neuron; (e) a refractory period, which represents the time period required for the accumulated variable in the neuron to rise to the resting value after firing of the neuron. These parameters may be predetermined and/or configurable and/or adjustable for each neuron. By adjusting for example the firing threshold, leakage rate, integration time constant, and refractory period of the neuron to match the energy content of a critical input signal feature, the neuron 1 will generate one or more precisely timed spikes when stimulated with an input signal containing that feature.

Configuration parameters of the synaptic elements 2 include the weight and gain of a synaptic element 2 . The weight of the synaptic element 2 is typically used to adjust the synaptic element 2 , while the gain of the synaptic element 2 is used for amplification of the signal in hardware and typically concerns a low pass filter implementation. Typically the gain is fixed at initialisation of the network 110 , while the weight can change based on the evolution/training of the spiking neural network 110 .

The microcontroller integrated circuit 100 further comprises a microprocessor core 101 to perform computations and control of the integrated circuit 100 . For example, the microprocessor core 101 can oversee the communication between the memory mapped control and configuration interface 113 and the memory device 102 .

The memory device 102 can be any computer-readable storage media. The memory device 102 may be non-transitory storage media. Illustrative computer-readable storage media include, but are not limited to: (i) non-writable storage media (e.g., read-only memory devices within a computer such as CD-ROM disks readable by a CD-ROM drive, ROM chips or any type of solid-state non-volatile semiconductor memory) on which information may be permanently stored; and (ii) writable storage media, e.g., hard disk drive or any type of solid-state random-access semiconductor memory, flash memory, on which alterable information may be stored.

External buses 104 are connected to one or multiple sensors or other data sources 103 . The microcontroller integrated circuit 100 can also be directly attached to sensors 105 . The sensors can first go through an analog-to-digital convertor 106 . One or multiple serial input/output ports 107 , and general purpose input/output ports 108 can be present on the microcontroller integrated circuit 100 . Direct access of external equipment can be arranged to the memory of the microcontroller integrated circuit 100 by direct memory access (DMA) 109 .

FIG. 3 shows the high-level architecture for learning systems with plurality of neuro-synaptic cores 210 arranged in an array of cores 200 . Each core 210 comprises a network of neurons 1 implemented in hardware, the neurons interconnected by synaptic elements 2 . A single core 210 may implement a complete spiking neural network, or a portion of a spiking neural network forming a separate sub-network. In this way, a large spiking neural network can be partitioned into a number of smaller sub-networks, each sub-network being implemented in one of the cores 210 of the array 200 . In one embodiment, the cores 210 may implement a spiking neural network 110 with associated input data ports 111 , output ports 112 , and/or control and configuration interface 113 shown in FIG. 2 .

By partitioning large spiking neural networks 110 into smaller sub-networks and implementing each of the sub-networks on one or more cores 210 , each with their own requisite circuitry, some of the non-idealities of circuits operating at smaller process geometries, and lower operating currents are mitigated, especially for large arrays. The core-based implementation approach thus reduces the impact of physical non-idealities.

A sub-network, or ensemble of neurons that form a co-operative group can for example form a classifier, an ensemble of classifiers, groups of neurons that handle data conversion, feature encoding or solely the classification, et cetera.

In such a regime, a large network of ensembles is partitioned and mapped onto an array of cores, each of which contains a programmable network of spiking neurons. Each core consequently implements a single ensemble, multiple small ensembles (in relation to the number of neurons and synapses in the core), or in the case of large ensembles, only a part of a single ensemble, with other parts implemented on other cores of the array. The modalities of how ensembles are partitioned and mapped to cores is determined by a mapping methodology. The mapping methodology can comprise a constraint-driven partitioning. The constraint can be a performance metric linked to the function of each respective sub-network. The performance metric could be dependent on power-area limitations, memory structures, memory access, time constants, biasing, technology restrictions, resilience, a level of accepted mismatch, and network or physical artifacts.

The periphery of the array 200 includes rows of the synaptic circuits which mimic the action of the soma and axon hillock of biological neurons. Further, each neuro-synaptic core 210 in the array 200 has a local router 202 , which communicates with the routers 202 of other cores 210 within a dedicated real-time reconfigurable network-on-chip.

The local routers 202 and their connections 201 form a programmable interconnect structure between the cores 210 of the core array 200 . The cores 210 are connected through a switchable matrix. The different cores 210 of the core array 200 are thus connected via the programmable interconnect structure. In particular, the different parts of the spiking neural network implemented on different cores 210 of the core array 200 are interconnected through the programmable interconnect structure. In this way, quantum effects and external noise only act on each core individually, but not on the network as a whole. Hence, these effects are mitigated.

The implemented spiking neural network 110 on the core array 200 can have high modularity, in the sense that the spiking neural network 110 has dense connections between the neurons within cores 210 but sparse connections between different cores 210 . In this way, noise and quantum effects are reduced even more between cores while still allowing for sub-networks to increase for example classification accuracy by allowing high complexity.

The programmable interconnect structure can form a packet switching network between the cores 210 in the core array 200 . For example, the local routers 202 can group data into packets that is then transmitted over the connections 201 . These connections 201 can form a digital network. Packets can be made of a header and a payload. Data in the header is used by the local routers 202 to direct the packet to its destination core 210 where the payload within the packet is extracted and used. The data can for example be output of one of the sub-networks of the spiking neural network that was partitioned and implemented on one or more cores 210 of the core array 200 . The data can also be input from a sensor or another external device.

The programmable interconnect structure could also use an address-event representation where the address of the neurons to be connected is send to a different core.

Furthermore, either synchronous or asynchronous communication could be used. An example of synchronous communication is any clock-based communication, while an example of asynchronous communication is for example a handshaking protocol.

The cores in the core array can form a network-on-chip on the microcontroller integrated circuit 100 . The network-on-chip improves the scalability and the power efficiency of the microcontroller integrated circuit 100 .

The topology for the Network-on-Chip, for example mesh, torus, tree, ring, star, is selected based on the parameters of the system. The routing algorithm in use depends on both the topology and the characteristics of the network 110 . The complexity of routing algorithms can be increased by, for example, considering multiple shortest routes to a target and, subsequently, selecting one of these paths randomly for each flit (resulting in better network load). Additional ef

CLAIMS

Claims ( 17 )

1 . A spiking neural network, comprising a spiking neuron, and a synaptic element connected to the spiking neuron,

wherein the synaptic element comprises a first and second receptor adapted to receive a synaptic input signal, wherein the first and second receptor respectively generate a first and second receptor signal on the basis of the synaptic input signal, wherein the synaptic element applies a weight to the first receptor signal to generate a synaptic output signal, the synaptic element being configurable to adjust the weight applied by the synaptic element at least on the basis of the second receptor signal, and wherein the spiking neuron is adapted to receive the synaptic output signal from the synaptic element, and generate a spatio-temporal spike train output signal at least in response to the received synaptic output signal.

2 . The spiking neural network of claim 1 , wherein the neuron emits a control signal, wherein the control signal adjusts, together with the second receptor signal, the weight applied by the synaptic element, preferably wherein the control signal is a back-propagating signal and/or wherein the control signal comprises one or more spikes generated by an action potential in the neuron.

3 . The spiking neural network of claim 2 , wherein the neuron comprises a dendrite, axon and soma, wherein the control signal stems from the dendrite and/or axon and/or soma of the neuron.

4 . The spiking neural network of claim 1 , wherein the decay time of the first receptor is faster than the decay time of the second receptor.

5 . The spiking neural network of claim 1 , wherein the first receptor generates a sourcing or sinking current for the spiking neuron; and/or wherein the first receptor comprises a low-pass filter.

6 . The spiking neural network of claim 1 , wherein the second receptor forms a voltage-gated receptor; and/or wherein the second receptor comprises a low-pass filter, band-pass filter, high-pass filter and/or amplifier.

7 . The spiking neural network of claim 1 , wherein the first receptor is an AMPA receptor or wherein the first receptor is a GABA receptor.

8 . The spiking neural network of claim 1 , wherein the second receptor is a NMDA receptor.

9 . A method for adjusting the weight of a synaptic element in a spiking neural network, the spiking neural network comprising a spiking neuron connected to the synaptic element,

wherein the synaptic element comprises a first and second receptor adapted to receive a synaptic input signal, wherein the first and second receptor receive the synaptic input signal and respectively generate a first and second receptor signal on the basis of the synaptic input signal, wherein the synaptic element applies a weight to the first receptor signal to generate a synaptic output signal, wherein on the basis of at least the second receptor signal the weight of the synaptic element is adjusted, and wherein the spiking neuron receives the synaptic output signal from the synaptic element and generates a spatio-temporal spike train output signal at least in response to the received synaptic output signal.

10 . The method of claim 9 , wherein the neuron emits a control signal, wherein the control signal adjusts, together with the second receptor signal, the weight applied by the synaptic element; preferably wherein the control signal is a back-propagating signal and/or wherein the control signal comprises one or more spikes generated by an action potential in the neuron.

11 . The method of claim 10 , wherein the neuron comprises a dendrite, axon and soma, wherein the control signal stems from the dendrite and/or axon and/or soma of the neuron.

12 . The method of claim 9 , wherein the decay time of the first receptor is faster than the decay time of the second receptor.

13 . The method of claim 9 , wherein the first receptor generates a sourcing or sinking current for the spiking neuron; and/or wherein the first receptor comprises a low-pass filter.

14 . The method of claim 9 , wherein the second receptor forms a voltage-gated receptor; and/or wherein the second receptor comprises a low-pass filter, band-pass filter, high-pass filter and/or amplifier.

15 . The method of claim 9 , wherein the first receptor is an AMPA receptor or wherein the first receptor is a GABA receptor.

16 . The method of claim 9 , wherein the second receptor is a NMDA receptor.

17 . An integrated circuit comprising the spiking neural network of claim 1 .

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