ABSTRACT
Abstract
In one embodiment, a method comprises receiving a selection of a neural network topology type; identifying a synapse memory mapping scheme for the selected neural network topology type from a plurality of synapse memory mapping schemes that are each associated with a respective neural network topology type; and mapping a plurality of synapse weights to locations in a memory based on the identified synapse memory mapping scheme.
Description
FIELD
The present disclosure relates in general to the field of computer development, and more specifically, to a neuromorphic computer with reconfigurable memory mapping for various neural network topologies.
BACKGROUND
A neural network may include a group of neurons loosely modeled after the structure of a biological brain which includes large clusters of neurons connected by synapses. In a neural network, neurons are connected to other neurons via links which may be excitatory or inhibitory in their effect on the activation state of connected neurons. A neuron may perform a function utilizing the values of its inputs to update a membrane potential of the neuron. A neuron may propagate a spike signal to connected neurons when a threshold associated with the neuron is surpassed. A neural network may be trained or otherwise adapted to perform various data processing tasks, such as computer vision tasks, speech recognition tasks, or other suitable computing tasks.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 illustrates a block diagram for an example computing system including a multicore processor that may implement a neural network in accordance with certain embodiments.
FIG. 2 illustrates a block diagram of a processor comprising a network on a chip (NoC) system that may implement a plurality of different neural networks having various topology types in accordance with certain embodiments.
FIG. 3 illustrates an example portion of a neural network in accordance with certain embodiments.
FIG. 4 illustrates an example system of neurosynaptic core clusters in accordance with certain embodiments.
FIG. 5A illustrates an example memory mapping scheme for a feed-forward neural network in accordance with certain embodiments.
FIG. 5B illustrates an example memory mapping scheme for a generative neural network in accordance with certain embodiments.
FIGS. 6A-6E illustrate example memory mapping schemes for a recurrent neural network in accordance with certain embodiments.
FIGS. 7A-7F illustrate example memory mapping schemes for a convolutional neural network in accordance with certain embodiments.
FIG. 8 depicts an example flow for mapping and accessing synapse weights in accordance with certain embodiments.
FIG. 9 depicts an example connection scheme of a portion of a neuromorphic processor in accordance with certain embodiments.
FIG. 10 illustrates a block diagram for an example computing system that may implement a plurality of different neural networks having various topology types in accordance with certain embodiments.
FIG. 11 illustrates an example neuromorphic processor 1100 in accordance with certain embodiments.
Like reference numbers and designations in the various drawings indicate like elements.
DETAILED DESCRIPTION
In the following description, numerous specific details are set forth, such as examples of specific types of processors and system configurations, specific hardware structures, specific architectural and micro architectural details, specific register configurations, specific instruction types, specific system components, specific measurements/heights, specific processor pipeline stages and operation etc. in order to provide a thorough understanding of the present disclosure. It will be apparent, however, to one skilled in the art that these specific details need not be employed to practice the present disclosure. In other instances, well known components or methods, such as specific and alternative processor architectures, specific logic circuits/code for described algorithms, specific firmware code, specific interconnect operation, specific logic configurations, specific manufacturing techniques and materials, specific compiler implementations, specific expression of algorithms in code, specific power down and gating techniques/logic and other specific operational details of computer system haven't been described in detail in order to avoid unnecessarily obscuring the present disclosure.
Although the following embodiments may be described with reference to specific integrated circuits, such as computing platforms or microprocessors, other embodiments are applicable to other types of integrated circuits and logic devices. Similar techniques and teachings of embodiments described herein may be applied to other types of circuits or semiconductor devices. For example, the disclosed embodiments may be used in various devices, such as server computer systems, desktop computer systems, handheld devices, tablets, other thin notebooks, systems on a chip (SOC) devices, and embedded applications. Some examples of handheld devices include cellular phones, Internet protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs. Embedded applications typically include a microcontroller, a digital signal processor (DSP), a system on a chip, network computers (NetPC), set-top boxes, network hubs, wide area network (WAN) switches, or any other system that can perform the functions and operations taught below. Moreover, the apparatuses, methods, and systems described herein are not limited to physical computing devices, but may also relate to software optimizations for energy conservation and efficiency.
Referring to FIG. 1 , an embodiment of a block diagram for a computing system including a multicore processor is depicted. Processor 100 includes any processor or processing device, such as a microprocessor, an embedded processor, a digital signal processor (DSP), a network processor, a handheld processor, an application processor, a co-processor, a system on a chip (SOC), or other device to execute code. Processor 100 , in one embodiment, includes at least two coresâ core
101 and 102 , which may include asymmetric cores or symmetric cores (the illustrated embodiment). However, processor 100 may include any number of processing elements that may be symmetric or asymmetric.
In one embodiment, a processing element refers to hardware or logic to support a software thread. Examples of hardware processing elements include: a thread unit, a thread slot, a thread, a process unit, a context, a context unit, a logical processor, a hardware thread, a core, and/or any other element, which is capable of holding a state for a processor, such as an execution state or architectural state. In other words, a processing element, in one embodiment, refers to any hardware capable of being independently associated with code, such as a software thread, operating system, application, or other code. A physical processor (or processor socket) typically refers to an integrated circuit, which potentially includes any number of other processing elements, such as cores or hardware threads.
A core often refers to logic located on an integrated circuit capable of maintaining an independent architectural state, wherein each independently maintained architectural state is associated with at least some dedicated execution resources. In contrast to cores, a hardware thread typically refers to any logic located on an integrated circuit capable of maintaining an independent architectural state, wherein the independently maintained architectural states share access to execution resources. As can be seen, when certain resources are shared and others are dedicated to an architectural state, the line between the nomenclature of a hardware thread and core overlaps. Yet often, a core and a hardware thread are viewed by an operating system as individual logical processors, where the operating system is able to individually schedule operations on each logical processor.
Physical processor 100 , as illustrated in FIG. 1 , includes two coresâ core
101 and 102 . Here, core
101 and 102 are considered symmetric cores, i.e. cores with the same configurations, functional units, and/or logic. In another embodiment, core 101 includes an out-of-order processor core, while core 102 includes an in-order processor core. However, cores
101 and 102 may be individually selected from any type of core, such as a native core, a software managed core, a core adapted to execute a native Instruction Set Architecture (ISA), a core adapted to execute a translated Instruction Set Architecture (ISA), a co-designed core, or other known core. In a heterogeneous core environment (i.e. asymmetric cores), some form of translation, such a binary translation, may be utilized to schedule or execute code on one or both cores. Yet to further the discussion, the functional units illustrated in core 101 are described in further detail below, as the units in core 102 operate in a similar manner in the depicted embodiment.
As depicted, core 101 includes two hardware threads
101 a and 101 b , which may also be referred to as hardware thread slots
101 a and 101 b . Therefore, software entities, such as an operating system, in one embodiment potentially view processor 100 as four separate processors, i.e., four logical processors or processing elements capable of executing four software threads concurrently. As alluded to above, a first thread is associated with architecture state registers 101 a , a second thread is associated with architecture state registers 101 b , a third thread may be associated with architecture state registers 102 a , and a fourth thread may be associated with architecture state registers 102 b . Here, each of the architecture state registers ( 101 a , 101 b , 102 a , and 102 b ) may be referred to as processing elements, thread slots, or thread units, as described above. As illustrated, architecture state registers 101 a are replicated in architecture state registers 101 b , so individual architecture states/contexts are capable of being stored for logical processor 101 a and logical processor 101 b . In core 101 , other smaller resources, such as instruction pointers and renaming logic in allocator and renamer block 130 may also be replicated for threads
101 a and 101 b . Some resources, such as re-order buffers in reorder/ retirement unit 135 , ILTB 120 , load/store buffers, and queues may be shared through partitioning. Other resources, such as general purpose internal registers, page-table base register(s), low-level data-cache and data-TLB 115 , execution unit(s) 140 , and portions of out-of- order unit 135 are potentially fully shared.
Processor 100 often includes other resources, which may be fully shared, shared through partitioning, or dedicated by/to processing elements. In FIG. 1 , an embodiment of a purely exemplary processor with illustrative logical units/resources of a processor is illustrated. Note that a processor may include, or omit, any of these functional units, as well as include any other known functional units, logic, or firmware not depicted. As illustrated, core 101 includes a simplified, representative out-of-order (OOO) processor core. But an in-order processor may be utilized in different embodiments. The OOO core includes a branch target buffer 120 to predict branches
FIELD
The present disclosure relates in general to the field of computer development, and more specifically, to a neuromorphic computer with reconfigurable memory mapping for various neural network topologies.
BACKGROUND
A neural network may include a group of neurons loosely modeled after the structure of a biological brain which includes large clusters of neurons connected by synapses. In a neural network, neurons are connected to other neurons via links which may be excitatory or inhibitory in their effect on the activation state of connected neurons. A neuron may perform a function utilizing the values of its inputs to update a membrane potential of the neuron. A neuron may propagate a spike signal to connected neurons when a threshold associated with the neuron is surpassed. A neural network may be trained or otherwise adapted to perform various data processing tasks, such as computer vision tasks, speech recognition tasks, or other suitable computing tasks.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 illustrates a block diagram for an example computing system including a multicore processor that may implement a neural network in accordance with certain embodiments.
FIG. 2 illustrates a block diagram of a processor comprising a network on a chip (NoC) system that may implement a plurality of different neural networks having various topology types in accordance with certain embodiments.
FIG. 3 illustrates an example portion of a neural network in accordance with certain embodiments.
FIG. 4 illustrates an example system of neurosynaptic core clusters in accordance with certain embodiments.
FIG. 5A illustrates an example memory mapping scheme for a feed-forward neural network in accordance with certain embodiments.
FIG. 5B illustrates an example memory mapping scheme for a generative neural network in accordance with certain embodiments.
FIGS. 6A-6E illustrate example memory mapping schemes for a recurrent neural network in accordance with certain embodiments.
FIGS. 7A-7F illustrate example memory mapping schemes for a convolutional neural network in accordance with certain embodiments.
FIG. 8 depicts an example flow for mapping and accessing synapse weights in accordance with certain embodiments.
FIG. 9 depicts an example connection scheme of a portion of a neuromorphic processor in accordance with certain embodiments.
FIG. 10 illustrates a block diagram for an example computing system that may implement a plurality of different neural networks having various topology types in accordance with certain embodiments.
FIG. 11 illustrates an example neuromorphic processor 1100 in accordance with certain embodiments.
Like reference numbers and designations in the various drawings indicate like elements.
DETAILED DESCRIPTION
In the following description, numerous specific details are set forth, such as examples of specific types of processors and system configurations, specific hardware structures, specific architectural and micro architectural details, specific register configurations, specific instruction types, specific system components, specific measurements/heights, specific processor pipeline stages and operation etc. in order to provide a thorough understanding of the present disclosure. It will be apparent, however, to one skilled in the art that these specific details need not be employed to practice the present disclosure. In other instances, well known components or methods, such as specific and alternative processor architectures, specific logic circuits/code for described algorithms, specific firmware code, specific interconnect operation, specific logic configurations, specific manufacturing techniques and materials, specific compiler implementations, specific expression of algorithms in code, specific power down and gating techniques/logic and other specific operational details of computer system haven't been described in detail in order to avoid unnecessarily obscuring the present disclosure.
Although the following embodiments may be described with reference to specific integrated circuits, such as computing platforms or microprocessors, other embodiments are applicable to other types of integrated circuits and logic devices. Similar techniques and teachings of embodiments described herein may be applied to other types of circuits or semiconductor devices. For example, the disclosed embodiments may be used in various devices, such as server computer systems, desktop computer systems, handheld devices, tablets, other thin notebooks, systems on a chip (SOC) devices, and embedded applications. Some examples of handheld devices include cellular phones, Internet protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs. Embedded applications typically include a microcontroller, a digital signal processor (DSP), a system on a chip, network computers (NetPC), set-top boxes, network hubs, wide area network (WAN) switches, or any other system that can perform the functions and operations taught below. Moreover, the apparatuses, methods, and systems described herein are not limited to physical computing devices, but may also relate to software optimizations for energy conservation and efficiency.
Referring to FIG. 1 , an embodiment of a block diagram for a computing system including a multicore processor is depicted. Processor 100 includes any processor or processing device, such as a microprocessor, an embedded processor, a digital signal processor (DSP), a network processor, a handheld processor, an application processor, a co-processor, a system on a chip (SOC), or other device to execute code. Processor 100 , in one embodiment, includes at least two coresâ core
101 and 102 , which may include asymmetric cores or symmetric cores (the illustrated embodiment). However, processor 100 may include any number of processing elements that may be symmetric or asymmetric.
In one embodiment, a processing element refers to hardware or logic to support a software thread. Examples of hardware processing elements include: a thread unit, a thread slot, a thread, a process unit, a context, a context unit, a logical processor, a hardware thread, a core, and/or any other element, which is capable of holding a state for a processor, such as an execution state or architectural state. In other words, a processing element, in one embodiment, refers to any hardware capable of being independently associated with code, such as a software thread, operating system, application, or other code. A physical processor (or processor socket) typically refers to an integrated circuit, which potentially includes any number of other processing elements, such as cores or hardware threads.
A core often refers to logic located on an integrated circuit capable of maintaining an independent architectural state, wherein each independently maintained architectural state is associated with at least some dedicated execution resources. In contrast to cores, a hardware thread typically refers to any logic located on an integrated circuit capable of maintaining an independent architectural state, wherein the independently maintained architectural states share access to execution resources. As can be seen, when certain resources are shared and others are dedicated to an architectural state, the line between the nomenclature of a hardware thread and core overlaps. Yet often, a core and a hardware thread are viewed by an operating system as individual logical processors, where the operating system is able to individually schedule operations on each logical processor.
Physical processor 100 , as illustrated in FIG. 1 , includes two coresâ core
101 and 102 . Here, core
101 and 102 are considered symmetric cores, i.e. cores with the same configurations, functional units, and/or logic. In another embodiment, core 101 includes an out-of-order processor core, while core 102 includes an in-order processor core. However, cores
101 and 102 may be individually selected from any type of core, such as a native core, a software managed core, a core adapted to execute a native Instruction Set Architecture (ISA), a core adapted to execute a translated Instruction Set Architecture (ISA), a co-designed core, or other known core. In a heterogeneous core environment (i.e. asymmetric cores), some form of translation, such a binary translation, may be utilized to schedule or execute code on one or both cores. Yet to further the discussion, the functional units illustrated in core 101 are described in further detail below, as the units in core 102 operate in a similar manner in the depicted embodiment.
As depicted, core 101 includes two hardware threads
101 a and 101 b , which may also be referred to as hardware thread slots
101 a and 101 b . Therefore, software entities, such as an operating system, in one embodiment potentially view processor 100 as four separate processors, i.e., four logical processors or processing elements capable of executing four software threads concurrently. As alluded to above, a first thread is associated with architecture state registers 101 a , a second thread is associated with architecture state registers 101 b , a third thread may be associated with architecture state registers 102 a , and a fourth thread may be associated with architecture state registers 102 b . Here, each of the architecture state registers ( 101 a , 101 b , 102 a , and 102 b ) may be referred to as processing elements, thread slots, or thread units, as described above. As illustrated, architecture state registers 101 a are replicated in architecture state registers 101 b , so individual architecture states/contexts are capable of being stored for logical processor 101 a and logical processor 101 b . In core 101 , other smaller resources, such as instruction pointers and renaming logic in allocator and renamer block 130 may also be replicated for threads
101 a and 101 b . Some resources, such as re-order buffers in reorder/ retirement unit 135 , ILTB 120 , load/store buffers, and queues may be shared through partitioning. Other resources, such as general purpose internal registers, page-table base register(s), low-level data-cache and data-TLB 115 , execution unit(s) 140 , and portions of out-of- order unit 135 are potentially fully shared.
Processor 100 often includes other resources, which may be fully shared, shared through partitioning, or dedicated by/to processing elements. In FIG. 1 , an embodiment of a purely exemplary processor with illustrative logical units/resources of a processor is illustrated. Note that a processor may include, or omit, any of these functional units, as well as include any other known functional units, logic, or firmware not depicted. As illustrated, core 101 includes a simplified, representative out-of-order (OOO) processor core. But an in-order processor may be utilized in different embodiments. The OOO core includes a branch target buffer 120 to predict branches to be executed/taken and an instruction-translation buffer (I-TLB) 120 to store address translation entries for instructions.
Core 101 further includes decode module 125 coupled to fetch unit 120 to decode fetched elements. Fetch logic, in one embodiment, includes individual sequencers associated with thread slots
101 a , 101 b , respectively. Usually core 101 is associated with a first ISA, which defines/specifies instructions executable on processor 100 . Often machine code instructions that are part of the first ISA include a portion of the instruction (referred to as an opcode), which references/specifies an instruction or operation to be performed. Decode logic 125 includes circuitry that recognizes these instructions from their opcodes and passes the decoded instructions on in the pipeline for processing as defined by the first ISA. For example, as discussed in more detail below decoders 125 , in one embodiment, include logic designed or adapted to recognize specific instructions, such as transactional instruction. As a result of the recognition by decoders 125 , the architecture or core 101 takes specific, predefined actions to perform tasks associated with the appropriate instruction. It is important to note that any of the tasks, blocks, operations, and methods described herein may be performed in response to a single or multiple instructions; some of which may be new or old instructions. Note decoders 126 , in one embodiment, recognize the same ISA (or a subset thereof). Alternatively, in a heterogeneous core environment, decoders 126 recognize a second ISA (either a subset of the first ISA or a distinct ISA).
In one example, allocator and renamer block 130 includes an allocator to reserve resources, such as register files (RFs) to store instruction processing results. However, threads
101 a and 101 b are potentially capable of out-of-order execution, where allocator and renamer block 130 also reserves other resources, such as reorder buffers to track instruction results. Unit 130 may also include a register renamer to rename program/instruction reference registers to other registers internal to processor 100 . Reorder/ retirement unit 135 includes components, such as the reorder buffers mentioned above, load buffers, and store buffers, to support out-of-order execution and later in-order retirement of instructions executed out-of-order.
Scheduler and execution unit(s) block 140 , in one embodiment, includes a scheduler unit to schedule instructions/operation on execution units. For example, a floating point instruction is scheduled on a port of an execution unit that has an available floating point execution unit. Register files associated with the execution units are also included to store information instruction processing results. Exemplary execution units include a floating point execution unit, an integer execution unit, a jump execution unit, a load execution unit, a store execution unit, and other known execution units.
Lower level data cache and data translation buffer (D-TLB) 150 are coupled to execution unit(s) 140 . The data cache is to store recently used/operated on elements, such as data operands, which are potentially held in memory coherency states. The D-TLB is to store recent virtual/linear to physical address translations. As a specific example, a processor may include a page table structure to break physical memory into a plurality of virtual pages.
Here, cores
101 and 102 share access to higher-level or further-out cache, such as a second level cache associated with on- chip interface 110 . Note that higher-level or further-out refers to cache levels increasing or getting further way from the execution unit(s). In one embodiment, higher-level cache is a last-level data cacheâlast cache in the memory hierarchy on processor 100 âsuch as a second or third level data cache. However, higher level cache is not so limited, as it may be associated with or include an instruction cache. A trace cacheâa type of instruction cacheâinstead may be coupled after decoder 125 to store recently decoded traces. Here, an instruction potentially refers to a macro-instruction (i.e. a general instruction recognized by the decoders), which may decode into a number of micro-instructions (micro-operations).
In the depicted configuration, processor 100 also includes on- chip interface module 110 . Historically, a memory controller, which is described in more detail below, has been included in a computing system external to processor 100 . In this scenario, on- chip interface 110 is to communicate with devices external to processor 100 , such as system memory 175 , a chipset (often including a memory controller hub to connect to memory 175 and an I/O controller hub to connect peripheral devices), a memory controller hub, a northbridge, or other integrated circuit. And in this scenario, bus 105 may include any known interconnect, such as multi-drop bus, a point-to-point interconnect, a serial interconnect, a parallel bus, a coherent (e.g. cache coherent) bus, a layered protocol architecture, a differential bus, and a GTL bus.
Memory 175 may be dedicated to processor 100 or shared with other devices in a system. Common examples of types of memory 175 include dynamic random access memory (DRAM), static random access memory (SRAM), non-volatile memory (NV memory), and other known storage devices. Note that device 180 may include a graphic accelerator, processor or card coupled to a memory controller hub, data storage coupled to an I/O controller hub, a wireless transceiver, a flash device, an audio controller, a network controller, or other known device.
Recently however, as more logic and devices are being integrated on a single die, such as SOC, each of these devices may be incorporated on processor 100 . For example in one embodiment, a memory controller hub is on the same package and/or die with processor 100 . Here, a portion of the core (an on-core portion) 110 includes one or more controller(s) for interfacing with other devices such as memory 175 or a graphics device 180 . The configuration including an interconnect and controllers for interfacing with such devices is often referred to as an on-core (or un-core configuration). As an example, on- chip interface 110 includes a ring interconnect for on-chip communication and a high-speed serial point-to- point link 105 for off-chip communication. Yet, in the SOC environment, even more devices, such as the network interface, co-processors, memory 175 , graphics processor 180 , and any other known computer devices/interface may be integrated on a single die or integrated circuit to provide small form factor with high functionality and low power consumption.
In one embodiment, processor 100 is capable of executing a compiler, optimization, and/or translator code 177 to compile, translate, and/or optimize application code 176 to support the apparatus and methods described herein or to interface therewith. A compiler often includes a program or set of programs to translate source text/code into target text/code. Usually, compilation of program/application code with a compiler is done in multiple phases and passes to transform hi-level programming language code into low-level machine or assembly language code. Yet, single pass compilers may still be utilized for simple compilation. A compiler may utilize any known compilation techniques and perform any known compiler operations, such as lexical analysis, preprocessing, parsing, semantic analysis, code generation, code transformation, and code optimization.
Larger compilers often include multiple phases, but most often these phases are included within two general phases: (1) a front-end, i.e. generally where syntactic processing, semantic processing, and some transformation/optimization may take place, and (2) a back-end, i.e. generally where analysis, transformations, optimizations, and code generation takes place. Some compilers refer to a middle, which illustrates the blurring of delineation between a front-end and back end of a compiler. As a result, reference to insertion, association, generation, or other operation of a compiler may take place in any of the aforementioned phases or passes, as well as any other known phases or passes of a compiler. As an illustrative example, a compiler potentially inserts operations, calls, functions, etc. in one or more phases of compilation, such as insertion of calls/operations in a front-end phase of compilation and then transformation of the calls/operations into lower-level code during a transformation phase. Note that during dynamic compilation, compiler code or dynamic optimization code may insert such operations/calls, as well as optimize the code for execution during runtime. As a specific illustrative example, binary code (already compiled code) may be dynamically optimized during runtime. Here, the program code may include the dynamic optimization code, the binary code, or a combination thereof.
Similar to a compiler, a translator, such as a binary translator, translates code either statically or dynamically to optimize and/or translate code. Therefore, reference to execution of code, application code, program code, or other software environment may refer to: (1) execution of a compiler program(s), optimization code optimizer, or translator either dynamically or statically, to compile program code, to maintain software structures, to perform other operations, to optimize code, or to translate code; (2) execution of main program code including operations/calls, such as application code that has been optimized/compiled; (3) execution of other program code, such as libraries, associated with the main program code to maintain software structures, to perform other software related operations, or to optimize code; or (4) a combination thereof.
FIG. 2 illustrates a block diagram of a processor 200 comprising a network on a chip (NoC) system that may implement a plurality of different neural networks having various topology types in accordance with certain embodiments. The processor 200 may include any processor or processing device, such as a microprocessor, an embedded processor, a digital signal processor (DSP), a network processor, a handheld processor, an application processor, a co-processor, an SoC, a hardware accelerator, or other device to execute code and/or perform other processing operations. In particular embodiments, processor 200 is implemented on a single die. Processor 200 may include any of the components of processor 100 and/or have any of the characteristics of processor 100 .
In the embodiment depicted, processor 200 includes a plurality of network elements 202 arranged in a grid network and coupled to each other with bi-directional links. However, an NoC in accordance with various embodiments of the present disclosure may be applied to any suitable network topologies (e.g., a hierarchical network or a ring network), sizes, bus widths, and processes. In the embodiment depicted, each network element 202 includes a router 204 and a core 208 (which in some embodiments may be a neuromorphic core), however in other embodiments, multiple cores from different network elements 202 may share a single router 204 . The routers 204 may be communicatively linked with one another in a network, such as a packet-switched network and/or a circuit-switched network, thus enabling communication between components (such as cores, storage elements, or other logic blocks) of the NoC that are connected to the routers. In the embodiment depicted, each router 204 is communicatively coupled to its own core 208 . In various embodiments, each router 204 may be communicatively coupled to multiple cores 208 (or other processing elements or logic blocks). As used herein, a reference to a core may also apply to other embodiments where a different logic block is used in place of a core. For example, various logic blocks may comprise a hardware accelerator (e.g., a graphics accelerator, multimedia accelerator, or video encode/decode accelerator), I/O block, memory controller, or other suitable fixed function logic. The processor 200 may include any number of processing elements or other logic blocks that may be symmetric or asymmetric. For example, the cores 208 of processor 200 may include asymmetric cores or symmetric cores. Processor 200 may include logic to operate as either or both of a packet-switched network and a circuit-switched network to provide intra-die communication.
In particular embodiments, packets may be communicated among the various routers 204 using resources of a packet-switched network. That is, the packet-switched network may provide communication between the routers (and their associated cores). The packets may include a control portion and a data portion. The control portion may include a destination address of the packet, and the data portion may contain the specific data to be communicated on the die 100 . For example, the control portion may include a destination address that corresponds to one of the network elements or cores of the die. In some embodiments, the packet-switched network includes buffering logic because a dedicated path is not assured from a source to a destination and so a packet may need to be stopped temporarily if two or more packets need to traverse the same link or interconnect. As an example, the packets may be buffered (e.g., by flip flops) at each of the respective routers as the packet travels from a source to a destination. In other embodiments, the buffering logic may be omitted and packets may be dropped when collision occurs. The packets may be received, transmitted and processed by the routers 204 . The packet-switched network may use point-to-point communication between neighboring routers. The control portions of the packets may be transferred between routers based on a packet clock, such as a 4 GHz clock. The data portion of the packets may be transferred between routers based on a similar clock, such as a 4 GHz clock.
In an embodiment, routers of processor 200 may be variously provided in two networks or communicate in two networks, such as a packet-switched network and a circuit-switched network. Such a communication approach may be termed a hybrid packet/circuit-switched network. In such embodiments, packets may be variously communicated among the various routers 204 using resources of the packet-switched network and the circuit-switched network. In order to transmit a single data packet, the circuit-switched network may allocate an entire path, whereas the packet-switched network may allocate only a single segment (or interconnect). In some embodiments, the packet-switched network may be utilized to reserve resources of the circuit-switched network for transmission of data between routers 204 .
Router 204 may include a plurality of port sets to variously couple to and communicate with adjoining network elements 202 . For example, circuit-switched and/or packet-switched signals may be communicated through these port sets. Port sets of router 204 may be logically divided, for example, according to the direction of adjoining network elements and/or the direction of traffic exchanges with such elements. For example, router 204 may include a north port set with input (âINâ) and output (âOUTâ) ports configured to (respectively) receive communications from and send communications to a network element 202 located in a ânorthâ direction with respect to router 204 . Additionally or alternatively, router 204 may include similar port sets to interface with network elements located to the south, west, east, or other direction. In the embodiment depicted, router 204 is configured for X first, Y second routing wherein data moves first in the East/West direction and then in the North/South direction. In other embodiments, any suitable routing scheme may be used.
In various embodiments, router 204 further comprises another port set comprising an input port and an output port configured to receive and send (respectively) communications from and to another agent of the network. In the embodiment depicted, this port set is shown at the center of router 204 . In one embodiment, these ports are for communications with logic that is adjacent to, is in communication with, or is otherwise associated with router 204 , such as logic of a âlocalâ core 208 . Herein, this port set will be referred to as a âcore port set,â though it may interface with logic other than a core in some implementations. In various embodiments, the core port set may interface with multiple cores (e.g., when multiple cores share a single router) or the router 204 may include multiple core port sets that each interface with a respective core. In another embodiment, this port set is for communications with a network element which is in a next level of a network hierarchy higher than that of router 204 . In one embodiment, the east and west directional links are on one metal layer, the north and south directional links on a second metal layer, and the core links on a third metal layer. In an embodiment, router 204 includes crossbar switching and arbitration logic to provide the paths of inter-port communication such as that shown in FIG. 2 . Logic (such as core 208 ) in each network element may have a unique clock and/or voltage or may share a clock and/or voltage with one or more other components of the NoC.
In particular embodiments, a core 208 of a network element may comprise a neuromorphic core including logic to implement one or more neurons and memory to store neural state parameters associated with the neurons. In various embodiments, a neuromorphic core may comprise any suitable logic for performing any of the functions described herein with respect to neurons. In particular embodiments, logic of a neuromorphic core that performs the functions of a neuron may be shared among multiple neurons of the core.
FIG. 3 illustrates an example portion of a neural network 300 in accordance with certain embodiments. Neural networks can learn unknown functions from training data and can perform a large number of classification and recognition tasks. Network graphs corresponding to neural networks have neurons as the vertices and synapses as the weighted edges. Neurons integrate inputs from a large number of fan-in synapses and then apply a transfer function to generate a single output. Spiking neurons may output a binary value based on a thresholding function. Neural networks are universal approximators. By choosing the synapse weights, an appropriately sized neural network can learn any task. The backwards propagation of action potentials (from a neuron to its fan-in neurons) can implement either undirected connections or enable learning rules like spike timing dependent plasticity (STDP).
In the illustrated embodiment, the neural network 300 includes neurons X 1 -X 9 . Neurons X 1 -X 4 are input neurons that respectively receive primary inputs I 1 -I 4 (which may be held constant while the neural network 300 processes an output). Any suitable primary inputs may be used. As one example, when neural network 300 performs image processing, a primary input value may be the value of a pixel from an image (and the value of the primary input may stay constant while the image is processed). As another example, when neural network 300 performs speech or video processing the primary input value applied to a particular input neuron may change over time based on changes to the input speech or video.
In the embodiment depicted, each link between two neurons has a synaptic weight indicating the strength of the relationship between the two neurons. The synapse weights are depicted as WXY, where X indicates the pre-synaptic neuron and Y indicates the post-synaptic neuron. Links between the neurons may be excitatory or inhibitory in their effect on the activation state of connected neurons. For example, a spike that propagates from X 1 to X 5 may increase or decrease the membrane potential of X 5 depending on the value of W 15 . In various embodiments, the connections may be directed or undirected.
In general, during each time-step, a neuron may receive any suitable inputs, such as a bias value or one or more input spikes from one or more other neurons. The bias value applied to a neuron may be a function of a primary input applied to an input neuron and/or some other value applied to a neuron (e.g., a constant value that may be adjusted during training or other operation of the neural network). In various embodiments, each neuron may be associated with its own bias value or a bias value could be applied to multiple neurons.
The neuron may perform a transfer function utilizing the values of its inputs and its current membrane potential. For example, the inputs may be added to the current membrane potential of the neuron to generate an updated membrane potential. As another example, a non-linear function, such as a sigmoid transfer function may be applied to the inputs and the current membrane potential. Any other suitable function may be used. The neuron then updates its membrane potential based on the output of the function. In some embodiments (e.g., in spiking neural networks), when the membrane potential of a neuron exceeds a threshold, the neuron may send spikes to each of its fan-out neurons (i.e., the neurons connected to the output of the spiking neuron). For example, when X 1 spikes, the spike (and the appropriate synapse weights) may be propagated to X 5 , X 6 , and X 7 . As another example, when X 5 spikes, the spikes (and the appropriate synapse weights) may be propagated to X 8 and X 9 (and in some embodiments to X 2 , X 3 , and X 4 if the neuron is configured to send backward spikes to its fan-in neurons).
In a particular embodiment, one or more memory arrays may comprise memory cells that store neural state parameters, such as synapse weights, membrane potentials, thresholds, outputs (e.g., the number of times that a neuron has spiked), bias amounts, or other values used during operation of the neural network 300 . The number of bits used for each of these values may vary depending on the implementation. In the examples illustrated below, specific bit lengths and/or component sizes (e.g., memory array sizes) may be described with respect to particular elements, but in other embodiments any suitable bit lengths and/or component sizes may be used.
The example of FIG. 3 provides a portion of just one example neural network topology of several known neural network topologies. Neural network topologies and machine learning algorithms may vary in their ability to perform applications such as speech recognition, financial data prediction, and object detection. Various different neural network topologies include, for example, neural networks with dense/sparse, structured/random, directed/undirected, or recurrent/feed forward connectivity. A hardware platform that may implement multiple different neural networks may benefit from reconfigurability, easy programmability, and low hardware overhead.
Typical neuromorphic computers may comprise tiles of cores. Each core contains a group of neurons and memory for fan-in synapses to those neurons. Within a core, synaptic connectivity is typically fully connected and directed (i.e., unidirectional) only. Output spikes from each core travel across the network to other cores. Such neuromorphic computers may be able to implement some dense and recurrent topologies. For example, these neuromorphic computers may be able to implement multi-layer perceptrons âMLPsâ and some other very simple topologies (e.g., Hopfield networks, winner take all âWTAâ networks) with acceptable overhead. However, to implement other topologies, large amounts of the synaptic memory would either be unused or replicated, leading to severe overhead due to synaptic memory being the primary area and energy component of the chip.
Various embodiments of the present disclosure provide a neuromorphic computer with a reconfigurable memory map and interconnection network that may be used to implement neural networks of various topologies or hierarchies of multiple neural network topologies. In various embodiments, the neuromorphic computer supports both sparse and dense connections between layers of neurons. The connectivity between neurons may be either structured or pseudorandom. The neuromorphic computer may enable either directed or undirected (unidirectional or bidirectional) synaptic connections between neurons. In various embodiments, the neuromorphic computer can implement MLPs, generative neural networks (e.g., Restricted Boltzmann Machines âRBMsâ or Deep Belief Networks âDBNsâ), feed-forward neural networks, recurrent neural networks (e.g., neural networks utilizing reservoir computing, such as Liquid State Machines âLSMsâ or Echo State Networks âESNsâ), convolutional neural networks âCNNsâ (e.g., deep CNNs, Convolutional DBNs), Hopfield networks, WTA networks, and/or other suitable neural network types. The neuromorphic computer may implement spiking neural networks (SNNs) or non-spiking neural networks (e.g., Artificial Neural networks).
Thus, various embodiments of the present disclosure may provide a reconfigurable neuromorphic computer that is capable of implementing (at any particular time) any one or more of various commonly used topologies for neural networks. In various embodiments, a neuromorphic computer connects neuron groups and synapse arrays in a multicast enabled network on chip (NoC). Various embodiments may utilize a com
CLAIMS
Claims ( 26 )
What is claimed is:
1. A processor comprising:
a memory to store a plurality of synapse weights of a neural network, the memory comprising a plurality of simultaneously accessible independent banks, a respective bank comprising a plurality of rows, a respective row comprising storage for at least one synapse weight;
at least one neuron core comprising logic associated with a plurality of neurons;
a synapse memory mapping engine to:
receive a selection of a neural network topology type;
identify a synapse memory mapping scheme for the selected neural network topology type from a plurality of synapse memory mapping schemes that are each associated with a respective neural network topology type; and
map the plurality of synapse weights to locations in the memory based on the identified synapse memory mapping scheme; and
when mapped to a first synapse memory mapping scheme, the plurality of banks are to store fan-out synapse weights representing weights of synapses between a neuron of a first layer and a plurality of neurons of a second layer such that a first parallel access of the plurality of banks at a first row is to output the fan-out synapse weights, and the plurality of banks are to store fan-in synapse weights representing weights of synapses between a neuron of the second layer and a plurality of neurons of the first layer such that a second parallel access of the plurality of banks at a different row for each bank accessed is to output the fan-in synapse weights.
2. The processor of claim 1 , wherein the first synapse memory mapping scheme of the plurality of synapse memory mapping schemes is associated with a first neural network topology type comprising a generative neural network and a second synapse memory mapping scheme of the plurality of synapse memory mapping schemes is associated with a second network topology type comprising a convolutional neural network.
3. The processor of claim 2 , wherein a third synapse memory mapping scheme of the plurality of synapse memory mapping schemes is associated with a third neural network topology type comprising a recurrent neural network.
4. The processor of claim 1 , wherein the processor is to access synapse weights connected to a neuron of the processor based on a memory address including at least one wildcard bit, wherein the memory address identifies locations in the memory of the synapse weights connected to the neuron.
5. The processor of claim 1 , wherein the identified synapse memory mapping scheme specifies a pseudorandom sparse connectivity scheme for a first group of rows of the memory.
6. The processor of claim 1 , wherein the identified synapse memory mapping scheme specifies a location for a synapse weight of the plurality of synapse weights based on an arithmetic operation including a position of the synapse weight within an ordered list of synapse weights and a position of a neuron connected to the synapse weight within an ordered list of neurons.
7. The processor of claim 1 , wherein the memory comprises a plurality of memory elements distributed among a plurality of synaptic cores of a network on chip.
8. A method comprising:
receiving a selection of a neural network topology type;
identifying a synapse memory mapping scheme for the selected neural network topology type from a plurality of synapse memory mapping schemes that are each associated with a respective neural network topology type; and
mapping a plurality of synapse weights to locations in a memory based on the identified synapse memory mapping scheme;
wherein the memory comprises a plurality of simultaneously accessible independent banks, a respective bank comprising a plurality of rows, a respective row comprising storage for at least one synapse weight; and
wherein, when mapped to a first synapse memory mapping scheme, the plurality of banks are to store fan-out synapse weights representing weights of synapses between a neuron of a first layer and a plurality of neurons of a second layer such that a first parallel access of the plurality of banks at a first row is to output the fan-out synapse weights, and the plurality of banks are to store fan-in synapse weights representing weights of synapses between a neuron of the second layer and a plurality of neurons of the first layer such that a second parallel access of the plurality of banks at a different row for each bank accessed is to output the fan-in synapse weights.
9. The method of claim 8 , wherein the first synapse memory mapping scheme of the plurality of synapse memory mapping schemes is associated with a first neural network topology type comprising a generative neural network and a second synapse memory mapping scheme of the plurality of synapse memory mapping schemes is associated with a second network topology type comprising a convolutional neural network.
10. The method of claim 9 , wherein a third synapse memory mapping scheme of the plurality of synapse memory mapping schemes is associated with a third neural network topology type comprising a recurrent neural network.
11. A non-transitory machine readable storage medium having instructions stored thereon, the instructions when executed by a machine to cause the machine to:
receive a selection of a neural network topology type;
identify a synapse memory mapping scheme for the selected neural network topology type from a plurality of synapse memory mapping schemes that are each associated with a respective neural network topology type; and
map a plurality of synapse weights to locations in a memory based on the identified synapse memory mapping scheme;
wherein the memory comprises a plurality of simultaneously accessible independent banks, a respective bank comprising a plurality of rows, a respective row comprising storage for at least one synapse weight; and
wherein, when mapped to a first synapse memory mapping scheme, the plurality of banks are to store fan-out synapse weights representing weights of synapses between a neuron of a first layer and a plurality of neurons of a second layer such that a first parallel access of the plurality of banks at a first row is to output the fan-out synapse weights, and the plurality of banks are to store fan-in synapse weights representing weights of synapses between a neuron of the second layer and a plurality of neurons of the first layer such that a second parallel access of the plurality of banks at a different row for each bank accessed is to output the fan-in synapse weights.
12. The medium of claim 11 , wherein the first synapse memory mapping scheme of the plurality of synapse memory mapping schemes is associated with a first neural network topology type comprising a generative neural network and a second synapse memory mapping scheme of the plurality of synapse memory mapping schemes is associated with a second network topology type comprising a convolutional neural network.
13. The medium of claim 12 , wherein a third synapse memory mapping scheme of the plurality of synapse memory mapping schemes is associated with a third neural network topology type comprising a recurrent neural network.
14. The medium of claim 11 , wherein the memory includes a plurality of independently accessible banks and the identified synapse memory mapping scheme specifies the storage of fan-out synapse weights of a first neuron in separate banks of the memory to enable parallel access of the fan-out synapse weights by the first neuron.
15. The medium of claim 11 , wherein the memory includes a plurality of independently accessible banks and the identified synapse memory mapping scheme specifies the storage of fan-in synapse weights of a first neuron in separate banks of the memory to enable parallel access of the fan-in synapse weights by the first neuron.
16. A system comprising:
a neuromorphic processor comprising:
a memory to store a plurality of synapse weights of a neural network, the memory comprising a plurality of simultaneously accessible independent banks, a respective bank comprising a plurality of rows, a respective row comprising storage for at least one synapse weight; and
logic to implement a plurality of neurons of the neural network;
an input/output interface; and
a synapse memory mapping engine to:
receive a selection of a neural network topology type, the selection to be received via the input/output interface;
identify a synapse memory mapping scheme for the selected neural network topology type from a plurality of synapse memory mapping schemes that are each associated with a respective neural network topology type; and
map the plurality of synapse weights to locations in the memory based on the identified synapse memory mapping scheme; and
when mapped to a first synapse memory mapping scheme, the plurality of banks are to store fan-out synapse weights representing weights of synapses between a neuron of a first layer and a plurality of neurons of a second layer such that a first parallel access of the plurality of banks at a first row is to output the fan-out synapse weights, and the plurality of banks are to store fan-in synapse weights representing weights of synapses between a neuron of the second layer and a plurality of neurons of the first layer such that a second parallel access of the plurality of banks at a different row for each bank accessed is to output the fan-in synapse weights.
17. The system of claim 16 , wherein the first synapse memory mapping scheme of the plurality of synapse memory mapping schemes is associated with a first neural network topology type comprising a generative neural network and a second synapse memory mapping scheme of the plurality of synapse memory mapping schemes is associated with second network topology type comprising a convolutional neural network.
18. The system of claim 17 , wherein a third synapse memory mapping scheme of the plurality of synapse memory mapping schemes is associated with a third neural network topology type comprising a recurrent neural network.
19. The system of claim 16 , wherein the memory includes a plurality of independently accessible banks and the identified synapse memory mapping scheme specifies the storage of fan-out synapse weights of a first neuron in separate banks of the memory to enable parallel access of the fan-out synapse weights by the first neuron.
20. The system of claim 16 , wherein the memory includes a plurality of independently accessible banks and the identified synapse memory mapping scheme specifies the storage of fan-in synapse weights of a first neuron in separate banks of the memory to enable parallel access of the fan-in synapse weights by the first neuron.
21. The processor of claim 1 , wherein the parallel access of the fan-out synapse weights by the first neuron or parallel access of the fan-in synapse weights by the first neuron comprises performing an XOR operation on an index specifying a row of the memory.
22. The processor of claim 1 , wherein a neuron core of the at least one neuron core is to access synapse weights connected to the first neuron based on a memory address including at least one wildcard bit, wherein the memory address identifies locations in the memory of the synapse weights connected to the first neuron.
23. The method of claim 8 ,
wherein the method further comprises accessing synapse weights connected to a neuron based on a memory address including at least one wildcard bit, wherein the memory address identifies locations in the memory of the synapse weights connected to the neuron, and
wherein address bits of the memory address are grouped into pairs to enable encoding of the at least one wildcard bit.
24. The processor of claim 1 , wherein the banks are collocated in a common synapse core, wherein the common synapse core includes a synapse array memory to store a plurality of synapse weights, logic to write synapse weights to the synapse array memory, and logic to access the synapse weights.
25. The processor of claim 1 , wherein a first bank of the banks is located in a first synapse core and a second bank of the banks is located in a second synapse core, wherein the first synapse core and the second synapse core each comprise a respective synapse array memory to store a plurality of synapse weights, logic to write synapse weights to the respective synapse array memory, and logic to access the synapse weights.
26. The processor of claim 1 , wherein the banks are respective static random access memories.
US15/394,897
2016-12-30
2016-12-30
Neuromorphic computer with reconfigurable memory mapping for various neural network topologies
Active
2039-11-09
US11062203B2
( en )
Priority Applications (2)
Application Number
Priority Date
Filing Date
Title
US15/394,897
US11062203B2
( en )
2016-12-30
2016-12-30
Neuromorphic computer with reconfigurable memory mapping for various neural network topologies
EP17203931.5A
EP3343465A1
( en )
2016-12-30
2017-11-27
Neuromorphic computer with reconfigurable memory mapping for various neural network topologies
Applications Claiming Priority (1)
Application Number
Priority Date
Filing Date
Title
US15/394,897
US11062203B2
( en )
2016-12-30
2016-12-30
Neuromorphic computer with reconfigurable memory mapping for various neural network topologies
Publications (2)
Publication Number
Publication Date
US20180189645A1
US20180189645A1 ( en )
2018-07-05
US11062203B2
true
US11062203B2 ( en )
2021-07-13
Family
ID=60480237
Family Applications (1)
Application Number
Title
Priority Date
Filing Date
US15/394,897
Active
2039-11-09
US11062203B2
( en )
2016-12-30
2016-12-30
Neuromorphic computer with reconfigurable memory mapping for various neural network topologies
Country Status (2)
Country
Link
US
( 1 )
US11062203B2
( en )
EP
( 1 )
EP3343465A1
( en )
Cited By (3)
* Cited by examiner, â Cited by third party
Publication number
Priority date
Publication date
Assignee
Title
US20210279571A1
( en )
*
2017-04-24
2021-09-09
Intel Corporation
Neural network optimization mechanism
US20220284279A1
( en )
*
2021-03-03
2022-09-08
X Development Llc
Computational techniques for identifying the surface of a brain
US12530562B2
( en )
2022-07-11
2026-01-20
Alibaba (China) Co., Ltd.
Chiplet-based hierarchical tree topology architecture for neuromorphic computing
Families Citing this family (40)
* Cited by examiner, â Cited by third party
Publication number
Priority date
Publication date
Assignee
Title
WO2015123658A1
( en )
2014-02-14
2015-08-20
Sonic Blocks, Inc.
Modular quick-connect a/v system and methods thereof
US10248906B2
( en )
*
2016-12-28
2019-04-02
Intel Corporation
Neuromorphic circuits for storing and generating connectivity information
US10922607B2
( en )
2016-12-30
2021-02-16
Intel Corporation
Event driven and time hopping neural network
US10713558B2
( en )
2016-12-30
2020-07-14
Intel Corporation
Neural network with reconfigurable sparse connectivity and online learning
CN113918481A
( en )
2017-07-30
2022-01-11
纽ç½å¸æå¾·æéå ¬å¸
Memory chip
GB2568776B
( en )
*
2017-08-11
2020-10-28
Google Llc
Neural network accelerator with parameters resident on chip
KR102610820B1
( en )
*
2017-09-27
2023-12-06
ì¼ì±ì ì주ìíì¬
Neural network system, and Operating method of neural network system
US10452540B2
( en )
*
2017-10-20
2019-10-22
International Business Machines Corporation
Memory-mapped interface for message passing computing systems
JP6794336B2
( en )
*
2017-11-17
2020-12-02
æ ªå¼ä¼ç¤¾æ±è
Neural network device
US11195079B2
( en )
*
2017-11-22
2021-12-07
Intel Corporation
Reconfigurable neuro-synaptic cores for spiking neural network
US11593623B2
( en )
*
2017-12-22
2023-02-28
Intel Corporation
Spiking neural network accelerator using external memory
US11150327B1
( en )
*
2018-01-12
2021-10-19
Hrl Laboratories, Llc
System and method for synthetic aperture radar target recognition using multi-layer, recurrent spiking neuromorphic networks
US12067481B2
( en )
2018-10-14
2024-08-20
International Business Machines Corporation
Array-integrated upstream/downstream router for circuit switched parallel connectivity
US11120561B2
( en )
*
2018-10-31
2021-09-14
International Business Machines Corporation
Detection, tracking and recognition on networks of digital neurosynaptic cores
US11468299B2
( en )
2018-11-01
2022-10-11
Brainchip, Inc.
Spiking neural network
US10735231B2
( en )
*
2018-12-19
2020-08-04
International Business Machines Corporation
Demodulating modulated signals with artificial neural networks
CN113597621A
( en )
*
2018-12-29
2021-11-02
å为ææ¯æéå ¬å¸
Computing resource allocation technique and neural network system
US11816563B2
( en )
2019-01-17
2023-11-14
Samsung Electronics Co., Ltd.
Method of enabling sparse neural networks on memresistive accelerators
CN110163338B
( en )
*
2019-01-31
2024-02-02
è ¾è®¯ç§æï¼æ·±å³ï¼æéå ¬å¸
Chip computing method, device, terminal and chip with computing array
EP3716154A1
( en )
*
2019-03-27
2020-09-30
GrAl Matter Labs S.A.S.
Neuromorphic processing system and method of operating the same
US11397895B2
( en )
2019-04-24
2022-07-26
X Development Llc
Neural network inference within physical domain via inverse design tool
KR102301041B1
( en )
*
2019-07-04
2021-09-14
íêµê³¼í기ì ì°êµ¬ì
Neuromorphic device
RU2739340C1
( en )
*
2019-11-14
2020-12-23
ФедеÑалÑное гоÑÑдаÑÑÑвенное бÑджеÑное ÑÑÑеждение наÑки ÐнÑÑиÑÑÑ Ñизиологии им. Ð.Ð. Ðавлова РоÑÑийÑкой академии наÑк (ÐФ Ð ÐÐ)
Method for neuromorphic data processing and device for implementation thereof
KR102832599B1
( en )
2019-11-15
2025-07-14
ì¼ì±ì ì주ìíì¬
Neuromorphic device based on memory
US11663043B2
( en )
*
2019-12-02
2023-05-30
Meta Platforms, Inc.
High bandwidth memory system with dynamically programmable distribution scheme
US11521085B2
( en )
2020-04-07
2022-12-06
International Business Machines Corporation
Neural network weight distribution from a grid of memory elements
CN111882050B
( en )
*
2020-07-20
2024-02-06
å¤æ¦å¤§å¦
FPGA-based design method for improving BCPNN speed
EP3944153A1
( en )
2020-07-24
2022-01-26
GrAl Matter Labs S.A.S.
Message based multi-processor system and method of operating the same
CN113485762B
( en )
*
2020-09-19
2024-07-26
广ä¸é«äºå导ä½ç§æè¡ä»½æéå ¬å¸
Method and apparatus for improving system performance by offloading computing tasks using configurable devices
US12406186B2
( en )
*
2020-10-21
2025-09-02
International Business Machines Corporation
Conflict-free, stall-free, broadcast network on chip
US20220129769A1
( en )
*
2020-10-22
2022-04-28
International Business Machines Corporation
Modular neural network computing apparatus with distributed neural network storage
CN112561042B
( en )
*
2021-03-01
2021-06-29
æµæ±å¤§å¦
A neural model mapping method for brain-like computer operating system
US11880448B1
( en )
*
2021-03-09
2024-01-23
National Technology & Engineering Solutions Of Sandia, Llc
Secure authentication using recurrent neural networks
US12266031B2
( en )
*
2021-04-28
2025-04-01
International Business Machines Corporation
Memory mapping of activations for convolutional neural network executions
US12518149B2
( en )
2021-09-29
2026-01-06
International Business Machines Corporation
Implicit vector concatenation within 2D mesh routing
CN114742214B
( en )
*
2022-03-25
2025-06-10
ä¸å±±å¤§å¦
A neural network high-speed caching method, system, device and storage medium
US20230394313A1
( en )
*
2022-06-02
2023-12-07
Actimize Ltd.
Ltp-induced online incremental deep learning
US20240028386A1
( en )
*
2022-07-21
2024-01-25
Mediatek Inc.
Deep neural network (dnn) compute loading and traffic-aware power management for multi-core artificial intelligence (ai) processing system
CN115834393B
( en )
*
2022-11-08
2025-09-19
å京çµæ±ç§ææéå ¬å¸
Method, system, electronic equipment and medium for determining route of bionic path
US12106209B1
( en )
*
2023-07-04
2024-10-01
Deepx Co., Ltd.
Method for evaluating an artificial neural network model performance and system using the same
Citations (10)
* Cited by examiner, â Cited by third party
Publication number
Priority date
Publication date
Assignee
Title
EP1356430A2
( en )
*
2000-10-13
2003-10-29
Fraunhofer-Gesellschaft Zur Förderung Der Angewandten Forschung E.V.
A method for supervised teaching of a recurrent artificial neural network
US20070165547A1
( en )
*
2003-09-09
2007-07-19
Koninklijke Philips Electronics N.V.
Integrated data processing circuit with a plurality of programmable processors
WO2015053889A2
( en )
2013-10-11
2015-04-16
Qualcomm Incorporated
Shared memory architecture for a neural simulator
US20160266975A1
( en )
*
2015-03-09
2016-09-15
Samsung Electronics Co., Ltd.
Memory devices and modules
EP3070649A2
( en )
2015-03-18
2016-09-21
International Business Machines Corporation
Implementing a neural network algorithm on a neurosynaptic substrate based on criteria related to the neurosynaptic substrate
US20180082181A1
( en )
*
2016-05-13
2018-03-22
Samsung Electronics, Co. Ltd.
Neural Network Reordering, Weight Compression, and Processing
US20180165575A1
( en )
*
2016-12-08
2018-06-14
Via Alliance Semiconductor Co., Ltd.
Neural network unit with mixed data and weight size computation capability
US20180174026A1
( en )
*
2016-12-20
2018-06-21
Michael I. Davies
Scalable neuromorphic core with shared synaptic memory and variable precision synaptic memory
US20180189648A1
( en )
2016-12-30
2018-07-05
Intel Corporation
Event driven and time hopping neural network
US20180189631A1
( en )
2016-12-30
2018-07-05
Intel Corporation
Neural network with reconfigurable sparse connectivity and online learning
2016
2016-12-30
US
US15/394,897
patent/US11062203B2/en
active
Active
2017
2017-11-27
EP
EP17203931.5A
patent/EP3343465A1/en
not_active
Withdrawn
Patent Citations (10)
* Cited by examiner, â Cited by third party
Publication number
Priority date
Publication date
Assignee
Title
EP1356430A2
( en )
*
2000-10-13
2003-10-29
Fraunhofer-Gesellschaft Zur Förderung Der Angewandten Forschung E.V.
A method for supervised teaching of a recurrent artificial neural network
US20070165547A1
( en )
*
2003-09-09
2007-07-19
Koninklijke Philips Electronics N.V.
Integrated data processing circuit with a plurality of programmable processors
WO2015053889A2
( en )
2013-10-11
2015-04-16
Qualcomm Incorporated
Shared memory architecture for a neural simulator
US20160266975A1
( en )
*
2015-03-09
2016-09-15
Samsung Electronics Co., Ltd.
Memory devices and modules
EP3070649A2
( en )
2015-03-18
2016-09-21
International Business Machines Corporation
Implementing a neural network algorithm on a neurosynaptic substrate based on criteria related to the neurosynaptic substrate
US20180082181A1
( en )
*
2016-05-13
2018-03-22
Samsung Electronics, Co. Ltd.
Neural Network Reordering, Weight Compression, and Processing
US20180165575A1
( en )
*
2016-12-08
2018-06-14
Via Alliance Semiconductor Co., Ltd.
Neural network unit with mixed data and weight size computation capability
US20180174026A1
( en )
*
2016-12-20
2018-06-21
Michael I. Davies
Scalable neuromorphic core with shared synaptic memory and variable precision synaptic memory
US20180189648A1
( en )
2016-12-30
2018-07-05
Intel Corporation
Event driven and time hopping neural network
US20180189631A1
( en )
2016-12-30
2018-07-05
Intel Corporation
Neural network with reconfigurable sparse connectivity and online learning
Non-Patent Citations (11)
* Cited by examiner, â Cited by third party
Title
EPO; Office Action issued in European Patent Application No. EP 17203931.5, dated Oct. 28, 2019; 7 pages.
Extended European Search Report issued in EP, Patent Application No. 17203931.5 dated May 2, 2018 (9 pages).
Francesco Galluppi, " A Hierachical Configuration System for a Massively Parallel Neural Hardware Platform ", May 15, 2012, 10 Pages (183-192), ISBN: 978-1-45-031215-8.
Jin, Xin. Efficient Modeling of Spiking Neural Networks on Scalable Chip Multiprocessor, 2008 IEEE International Joint Conference on Neural Networks (IEEE World Congress on Computational Intelligence), Hong Kong, 2008, pp. 2812-2819. (Year: 2008).
*
Kim, Duckhwan. " Neurocube: A Programmable Digital Neuromorphic Architecture with High-Density 3D Memory, " ACM SIGARCH Computer Architecture News, vol. 33, Jun. 2016, pp. 380-392. (Year: 2016).
*
Nageswaran, Jayram. " A Configurable Simulation Environment for the Efficient Simulation of Large-Scale Spiking Neural Networks on Graphics Processors, " Neural Networks 22, 2009, pp. 791-800) (Year: 2009).
*
U.S. Appl. No. 14/757,397, filed Dec. 23, 2015, entitled " Interconnection Scheme for Reconfigurable Neuromorphic Hardware, " inventors Gregory Chen, et al.
U.S. Appl. No. 15/088,543, filed Apr. 1, 2016, entitled " Digital Neuromorphic Processor Design with Large Fan-in/out On-Chip Learning, " inventors Gregory Chen, et al.
U.S. Appl. No. 15/392,407, filed Dec. 28, 2016, entitled " Neuromorphic Circuits for Sparse and Reconfigurable Connectivity, " inventors Huseyin Ekin Sumbul, et al.
U.S. Appl. No. 15/394,976, filed Dec. 30, 2016, entitled " Event Driven and Time Hopping Neural Network, " inventors Abhronil Sengupta, et al.
U.S. Appl. No. 15/395,231, filed Dec. 30, 2016, entitled " Neural Network With Reconfigurable Sparse Connectivity and Online Learning, " inventors Huseyin Ekin Sumbul, et al.
Cited By (4)
* Cited by examiner, â Cited by third party
Publication number
Priority date
Publication date
Assignee
Title
US20210279571A1
( en )
*
2017-04-24
2021-09-09
Intel Corporation
Neural network optimization mechanism
US12412086B2
( en )
*
2017-04-24
2025-09-09
Intel Corporation
Neural network optimization mechanism
US20220284279A1
( en )
*
2021-03-03
2022-09-08
X Development Llc
Computational techniques for identifying the surface of a brain
US12530562B2
( en )
2022-07-11
2026-01-20
Alibaba (China) Co., Ltd.
Chiplet-based hierarchical tree topology architecture for neuromorphic computing
Also Published As
Publication number
Publication date
EP3343465A1
( en )
2018-07-04
US20180189645A1
( en )
2018-07-05
Similar Documents
Publication
Publication Date
Title
EP3343465A1
( en )
2018-07-04
Neuromorphic computer with reconfigurable memory mapping for various neural network topologies
US10713558B2
( en )
2020-07-14
Neural network with reconfigurable sparse connectivity and online learning
US11195079B2
( en )
2021-12-07
Reconfigurable neuro-synaptic cores for spiking neural network
US10922607B2
( en )
2021-02-16
Event driven and time hopping neural network
Frenkel et al.
2019
MorphIC: A 65-nm 738k-synapse/mm $^ 2$ quad-core binary-weight digital neuromorphic processor with stochastic spike-driven online learning
US11055613B2
( en )
2021-07-06
Method and apparatus for a binary neural network mapping scheme utilizing a gate array architecture
US12585466B2
( en )
2026-03-24
In-memory computing processor, processing system, processing apparatus, deployment method of algorithm model
US11593623B2
( en )
2023-02-28
Spiking neural network accelerator using external memory
JP7242998B2
( en )
2023-03-22
Neuromorphic accelerator multitasking
US10748060B2
( en )
2020-08-18
Pre-synaptic learning using delayed causal updates
CN105718390B
( en )
2018-12-18
Low-power in shared memory link enters
CN109583578B
( en )
2025-07-29
Global and local time step determination scheme for neural networks
CN108604209B
( en )
2023-08-04
flat port bridge
US20220222513A1
( en )
2022-07-14
Neural network processor system and methods of operating and forming thereof
US10360496B2
( en )
2019-07-23
Apparatus and method for a digital neuromorphic processor
CN109582998B
( en )
2025-03-28
Root Complex Integrated Endpoint Emulation for Compact PCIe Endpoints
CN107005492B
( en )
2021-12-07
System for multicast and reduced communication over a network on a chip
Wu et al.
2010
A multicast routing scheme for a universal spiking neural network architecture
EP3343462B1
( en )
2021-04-21
Scalable free-running neuromorphic computer
Bogdan et al.
2019
Taming extreme heterogeneity via machine learning based design of autonomous manycore systems
Aichroth et al.
2021
SEC-Learn: Sensor Edge Cloud for Federated Learning
Johnson et al.
2022
SEC-Learn: Sensor Edge Cloud for Federated Learning
Su
2025
Design Principles for Energy and Memory Efficient Neuromorphic Architectures
Streat
2016
A Scalable Flash-Based Hardware Architecture for the Hierarchical Temporal Memory Spatial Pooler
WO2020121203A1
( en )
2020-06-18
Realigning streams of neuron outputs in artificial neural network computations
Legal Events
Date
Code
Title
Description
2017-01-17
AS
Assignment
Owner name : INTEL CORPORATION, CALIFORNIA
Free format text : ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHEN, GREGORY K.;KUMAR, RAGHAVAN;SUMBUL, HUSEYIN EKIN;AND OTHERS;REEL/FRAME:040989/0479
Effective date : 20170110
2017-03-06
STPP
Information on status: patent application and granting procedure in general
Free format text : DOCKETED NEW CASE - READY FOR EXAMINATION
2020-02-28
STPP
Information on status: patent application and granting procedure in general
Free format text : NON FINAL ACTION MAILED
2020-07-17
STPP
Information on status: patent application and granting procedure in general
Free format text : FINAL REJECTION MAILED
2020-11-30
STPP
Information on status: patent application and granting procedure in general
Free format text : DOCKETED NEW CASE - READY FOR EXAMINATION
2021-03-19
STPP
Information on status: patent application and granting procedure in general
Free format text : NOTICE OF ALLOWANCE MAILED -- APPLICATION RECEIVED IN OFFICE OF PUBLICATIONS
2021-06-09
STPP
Information on status: patent application and granting procedure in general
Free format text : PUBLICATIONS -- ISSUE FEE PAYMENT RECEIVED
2021-06-10
STPP
Information on status: patent application and granting procedure in general
Free format text : PUBLICATIONS -- ISSUE FEE PAYMENT VERIFIED
<time itemprop="date" datet