ABSTRACT
Abstract
Error correcting memory systems and methods of operating the memory systems are disclosed. In some embodiments, a memory system includes: a data memory; an ECC memory; and a data scrubbing circuit electrically coupled to the ECC memory and the data memory. The data scrubbing circuit may be configured to, in response to receiving a scrub data command, correct an error in the data memory. A code word length used to correct the error may be longer than a word length used during normal access of the data memory. In some embodiments, a memory system includes a first memory circuit associated with a first bit error rate and a second memory circuit associated with a second bit error rate. In some embodiments, a memory system includes an error correctable multi-level cell (MLC) array.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
This Application is a continuation of U.S. application Ser. No. 17/554,505, filed Dec. 17, 2021, which is a continuation of U.S. application Ser. No. 17/284,642, filed Apr. 12, 2021, now U.S. Pat. No. 11,204,835, which is a national stage application under 35 U.S.C. § 371 of International Application No. PCT/US2019/055963, filed internationally on Oct. 11, 2019, which claims the benefit of U.S. Provisional Application No. 62/745,204, filed on Oct. 12, 2018, U.S. Provisional Application No. 62/755,702, filed on Nov. 5, 2018, and U.S. Provisional Application No. 62/886,967, filed on Aug. 15, 2019, the entire disclosures of which are herein incorporated by reference in their entireties and for all purposes.
FIELD
This disclosure generally relates to computing memory. More specifically, this disclosure relates to devices and method for computing memory error correction.
BACKGROUND
Magnetic-Random-Access-Memory (MRAM), Phase-Change-Memory (PCM), Resistive-Random-Access-Memory (RRAM), and Ferroelectric-Random-Access-Memory (FRAM) are some of the non-volatile memory technologies that may have faster programming and higher re-write endurance than FLASH. For example, high performance MRAM may be used in edge-AI applications, which may require complex data structure after model optimization.
To achieve high performance, a number of unique circuit challenges exist for non-volatile memory like MRAM. Particularly, the read performance may be limited by read-disturb error at higher voltage operation, and write performance may be limited by hard break down at even higher voltage operation. Another obstacle may be that higher level of error correction may be required to achieve long-term data retention at higher temperature or during higher temperature events. In these instances, a two-bit correcting circuit may be used, but the circuit may add additional delays to read and write operations.
Furthermore, some of these non-volatile RAM technologies and conventional volatile memory technologies may be sensitive to environmental disturbances. For example, data in DRAM is sensitive to high temperature exor ionizing radiation, and data in MRAM may be corrupted by high temperature or large magnetic field.
Power may be a major constraint for electronic device design, and memory devices may consume an increasing portion of the total power, as memory density continues to increase. Reducing memory power consumption may increase error rate for retaining data and for read and write operations.
Large area overhead may be required to achieve adequate error correction strength. For example, using the low-latency hamming code, five error correction code (ECC) bits may be required to protect an 8-bit word against a single bit error. As another example, larger blocks of data (e.g., 1024 bits or more) may be protected with less ECC check bits using the Bose, Chaudhuri, and Hocquenghem (BCH) code or low-density parity check (LDPC) code. But these ECC codes require more complex encoding and decoding operations, and may affect performance.
Multi-level cell (MLC) devices (such as floating gate or charge-trapping FLASH device, eDRAM capacitors, RRAM, PCM, analog memory) may be used to perform compute-in-memory operations by representing the matrix multiplicand with multiple states or a continuum of analog characteristics. However, most of these devices may exhibit drift during operation that may gradually change the value of the matrix multiplicand. If the device drifts beyond a threshold, it may be difficult for to simply âread and recoverâ and maintain a correct value over time.
SUMMARY
Disclosed herein are error correcting memory systems and methods of operating the memory systems. In some embodiments, a memory system includes: a data memory; an ECC memory; and a data scrubbing circuit electrically coupled to the ECC memory and the data memory. The data scrubbing circuit may be configured to, in response to receiving a scrub data command, correct an error in the data memory. A code word length used to correct the error may be longer than a word length used during normal access of the data memory. In some embodiments, a memory system includes a first memory circuit associated with a first bit error rate and a second memory circuit associated with a second bit error rate. In some embodiments, a memory system includes an error correctable multi-level cell (MLC) array.
In some embodiments, a memory system comprises: a data memory; an ECC memory; and a data scrubbing circuit electrically coupled to the ECC memory and the data memory.
In some embodiments, the data scrubbing circuit is configured to, in response to receiving a scrub data command, correct an error in the data memory.
In some embodiments, a code word length used to correct the error is longer than a word length used during normal access of the data memory
In some embodiments, the data scrubbing circuit comprises a data buffer, a data scrubbing controller, an ECC encoding circuit, and an ECC decoding circuit.
In some embodiments, the data scrubbing circuit is configured to correct the error in the data memory while the data memory is concurrently accessed.
In some embodiments, the memory system further comprises an environmental disturbance sensor configured to detect an environmental condition, and wherein the data scrubbing circuit generates a scrub data command based on the detected environmental condition.
In some embodiments, the environmental condition includes at least one of a temperature and a magnetic field.
In some embodiments, the data scrubbing circuit is configured to detect change in known data and generate a scrub data command based on the detection of the change.
In some embodiments, the memory system further comprises a timer circuit configured to: track a time lapsed; and determine whether the time lapsed is greater than a timing threshold, and the scrub data command is generated in accordance with the determination that the time lapsed is greater than the timing threshold.
In some embodiments, the ECC memory includes a plurality of partitions, and the data memory includes a plurality of ranges of memory addresses, each partition corresponding to a range of memory addresses in the data memory.
In some embodiments, the ECC memory includes a partition having a number of ECC bits, and the number of ECC bits is based on an ECC encoding method associated with a data scrubbing algorithm.
In some embodiments, the ECC memory includes a set of registers, wherein: each register corresponds to an ECC code word, each ECC code word corresponds to a section in the data memory, and each register stores a state of the section.
In some embodiments, at least one selected from the data memory and the ECC memory comprises magnetic random-access memory (MRAM).
In some embodiments, at least one selected from the data memory and the ECC memory include a memory unit cell including a magnetic tunnel junction (MTJ) having a property selected from reduced dimension, reduced coercive field, reduced magnetic anisotropy, and reduced saturation magnetization compared to a memory unit cell having a bit error rate between 10 â12 and 10 â2 .
In some embodiments, the MJT has two properties selected from reduced dimension, reduced coercive field, reduced magnetic anisotropy, and reduced saturation magnetization compared to a memory unit cell having a bit error rate between 10 â12 and 10 â2 .
In some embodiments, the data memory includes static random-access memory (SRAM), dynamic random-access memory (DRAM), or embedded DRAM (eDRAM).
In some embodiments, the data scrubbing circuit or a host is configured to determine whether the data memory is protected, and the ECC memory is configured to: in accordance with a determination that the data memory is protected, store ECC check-bits; and in accordance with a determination that the data memory is not protected, store computing data.
In some embodiments, the data memory and the ECC memory are included in different memory circuits.
In some embodiments, the data memory and the ECC memory are included in a same memory circuit.
In some embodiments, the memory system is electrically coupled to a host device.
In some embodiments, the data memory and the ECC memory include a memory unit cell including a MTJ having a size between 20 nm and 200 nm and a MOS transistor having a width-to-length ratio between 1 and 200.
In some embodiments, the data scrubbing circuit is configured to: receive a protect command for data; and in response to receiving the protect command, for each data word in the data to be protected: identify an address for a data code word associated with the data word; determine, based on the address, whether the data word is in a data memory; in response to determining that the data word is in the data memory, read the data word from the data memory; in response to determining that the data word is not in the data memory: receive the data word; and write the data word to the data memory; perform ECC encoding computation on the data word; generate the data code word based on the ECC encoding computation; write the data code word to the data memory at the address; generate ECC check bits based on the ECC encoding computation; and write the generated ECC check bits to a corresponding partition in the ECC memory.
In some embodiments, the data scrubbing circuit is configured to: receive a scrub data command; in response to receiving the scrub data command, for each data word to be scrubbed: identify: a starting address for a data code word, and a corresponding ECC memory partition; read a data word associated with the starting address from a data memory; read ECC check bits associated with the corresponding ECC memory partition from an ECC memory; perform ECC decoding computation based on the data word and ECC check bits; determine whether the data word includes an error based on the ECC decoding computation; in response to determining that the data word includes the error, replace error bits with correctable error bits in the data word, wherein the data word including the correctable error bits is a scrubbed data word; in response to determining that the data word does not include the error, forgo replacing the error bits with the correctable error bits in the data word, wherein the data word is the scrubbed data word; determine whether the scrubbed data word is requested by a host; in response to determining that the scrubbed data is requested by the host, output the scrubbed data word to a memory controller electrically coupled to the host; and in response to determining that the scrubbed data is not requested by the host, forgo outputting the scrubbed data word to the memory controller.
In some embodiments, a method of operating a memory system, the memory system comprising: a data memory; an ECC memory; and a data scrubbing circuit electrically coupled to the ECC memory and the data memory, the method comprises: in response to receiving a scrub data command, correcting, using the data scrubbing circuit, an error in the data memory.
In some embodiments, a code word length used to correct the error is longer than a word length used during normal access of the data memory.
In some embodiments, the data scrubbing circuit comprises a data buffer, a data scrubbing controller, an ECC encoding circuit, and an ECC decoding circuit.
In some embodiments, the method further comprises concurrently accessing the data memory while correcting the error in the data memory.
In some embodiments, the method further comprises detecting an environmental condition, using an environmental disturbance sensor; and generating the scrub data command based on the detected environmental condition.
In some embodiments, the environmental condition includes at least one of a temperature and a magnetic field.
In some embodiments, the method further comprises detecting change in known data; and generating the scrub data command based on the detection of the change.
In some embodiments, the method further comprises tracking a time lapsed; determining whether the time lapsed is greater than a timing threshold, and generating the scrub data command in accordance with the determination that the time lapsed is greater than the timing threshold.
In some embodiments, the ECC memory includes a plurality of partitions, and the data memory includes a plurality of ranges of memory addresses, each partition corresponding to a range of memory addresses in the data memory.
In some embodiments, the ECC memory includes a partition having a number of ECC bits associated with a data scrubbing algorithm, the method further comprising performing an ECC encoding method using the number of ECC bits.
In some embodiments, the ECC memory includes a set of registers, wherein: each register corresponds to an ECC code word, each ECC code word corresponds to a section in the data memory, and each register stores a state of the section.
In some embodiments, at least one selected from the data memory and the ECC memory comprises magnetic random-access memory (MRAM).
In some embodiments, at least one selected from the data memory and the ECC memory include a memory unit cell including a magnetic tunnel junction (MTJ) having a property selected from reduced dimension, reduced coercive field, reduced magnetic anisotropy, and reduced saturation magnetization compared to a memory unit cell having a bit error rate between 10 â12 and 10 â2 .
In some embodiments, the MJT has two properties selected from reduced dimension, reduced coercive field, reduced magnetic anisotropy, and reduced saturation magnetization compared to a memory unit cell having a bit error rate between 10 â12 and 10 â2 .
In some embodiments, the data memory includes static random-access memory (SRAM), dynamic random-access memory (DRAM), or embedded DRAM (eDRAM).
In some embodiments, the method further comprises determining whether the data memory is protected; in accordance with a determination that the data memory is protected, storing ECC check-bits in the ECC memory; and in accordance with a determination that the data memory is not protected, store computing data in the ECC memory.
In some embodiments, the data memory and the ECC memory are included in different memory circuits.
In some embodiments, the data memory and the ECC memory are included in a same memory circuit.
In some embodiments, the memory system is electrically coupled to a host device.
In some embodiments, the data memory and the ECC memory include a memory unit cell including a MTJ having a size between 20 nm and 200 nm and a MOS transistor having a width-to-length ratio between 1 and 200.
In some embodiments, the method further comprises receiving a protect command for data; and in response to receiving the protect command, for each data word in the data to be p
CROSS REFERENCE TO RELATED APPLICATIONS
This Application is a continuation of U.S. application Ser. No. 17/554,505, filed Dec. 17, 2021, which is a continuation of U.S. application Ser. No. 17/284,642, filed Apr. 12, 2021, now U.S. Pat. No. 11,204,835, which is a national stage application under 35 U.S.C. § 371 of International Application No. PCT/US2019/055963, filed internationally on Oct. 11, 2019, which claims the benefit of U.S. Provisional Application No. 62/745,204, filed on Oct. 12, 2018, U.S. Provisional Application No. 62/755,702, filed on Nov. 5, 2018, and U.S. Provisional Application No. 62/886,967, filed on Aug. 15, 2019, the entire disclosures of which are herein incorporated by reference in their entireties and for all purposes.
FIELD
This disclosure generally relates to computing memory. More specifically, this disclosure relates to devices and method for computing memory error correction.
BACKGROUND
Magnetic-Random-Access-Memory (MRAM), Phase-Change-Memory (PCM), Resistive-Random-Access-Memory (RRAM), and Ferroelectric-Random-Access-Memory (FRAM) are some of the non-volatile memory technologies that may have faster programming and higher re-write endurance than FLASH. For example, high performance MRAM may be used in edge-AI applications, which may require complex data structure after model optimization.
To achieve high performance, a number of unique circuit challenges exist for non-volatile memory like MRAM. Particularly, the read performance may be limited by read-disturb error at higher voltage operation, and write performance may be limited by hard break down at even higher voltage operation. Another obstacle may be that higher level of error correction may be required to achieve long-term data retention at higher temperature or during higher temperature events. In these instances, a two-bit correcting circuit may be used, but the circuit may add additional delays to read and write operations.
Furthermore, some of these non-volatile RAM technologies and conventional volatile memory technologies may be sensitive to environmental disturbances. For example, data in DRAM is sensitive to high temperature exor ionizing radiation, and data in MRAM may be corrupted by high temperature or large magnetic field.
Power may be a major constraint for electronic device design, and memory devices may consume an increasing portion of the total power, as memory density continues to increase. Reducing memory power consumption may increase error rate for retaining data and for read and write operations.
Large area overhead may be required to achieve adequate error correction strength. For example, using the low-latency hamming code, five error correction code (ECC) bits may be required to protect an 8-bit word against a single bit error. As another example, larger blocks of data (e.g., 1024 bits or more) may be protected with less ECC check bits using the Bose, Chaudhuri, and Hocquenghem (BCH) code or low-density parity check (LDPC) code. But these ECC codes require more complex encoding and decoding operations, and may affect performance.
Multi-level cell (MLC) devices (such as floating gate or charge-trapping FLASH device, eDRAM capacitors, RRAM, PCM, analog memory) may be used to perform compute-in-memory operations by representing the matrix multiplicand with multiple states or a continuum of analog characteristics. However, most of these devices may exhibit drift during operation that may gradually change the value of the matrix multiplicand. If the device drifts beyond a threshold, it may be difficult for to simply âread and recoverâ and maintain a correct value over time.
SUMMARY
Disclosed herein are error correcting memory systems and methods of operating the memory systems. In some embodiments, a memory system includes: a data memory; an ECC memory; and a data scrubbing circuit electrically coupled to the ECC memory and the data memory. The data scrubbing circuit may be configured to, in response to receiving a scrub data command, correct an error in the data memory. A code word length used to correct the error may be longer than a word length used during normal access of the data memory. In some embodiments, a memory system includes a first memory circuit associated with a first bit error rate and a second memory circuit associated with a second bit error rate. In some embodiments, a memory system includes an error correctable multi-level cell (MLC) array.
In some embodiments, a memory system comprises: a data memory; an ECC memory; and a data scrubbing circuit electrically coupled to the ECC memory and the data memory.
In some embodiments, the data scrubbing circuit is configured to, in response to receiving a scrub data command, correct an error in the data memory.
In some embodiments, a code word length used to correct the error is longer than a word length used during normal access of the data memory
In some embodiments, the data scrubbing circuit comprises a data buffer, a data scrubbing controller, an ECC encoding circuit, and an ECC decoding circuit.
In some embodiments, the data scrubbing circuit is configured to correct the error in the data memory while the data memory is concurrently accessed.
In some embodiments, the memory system further comprises an environmental disturbance sensor configured to detect an environmental condition, and wherein the data scrubbing circuit generates a scrub data command based on the detected environmental condition.
In some embodiments, the environmental condition includes at least one of a temperature and a magnetic field.
In some embodiments, the data scrubbing circuit is configured to detect change in known data and generate a scrub data command based on the detection of the change.
In some embodiments, the memory system further comprises a timer circuit configured to: track a time lapsed; and determine whether the time lapsed is greater than a timing threshold, and the scrub data command is generated in accordance with the determination that the time lapsed is greater than the timing threshold.
In some embodiments, the ECC memory includes a plurality of partitions, and the data memory includes a plurality of ranges of memory addresses, each partition corresponding to a range of memory addresses in the data memory.
In some embodiments, the ECC memory includes a partition having a number of ECC bits, and the number of ECC bits is based on an ECC encoding method associated with a data scrubbing algorithm.
In some embodiments, the ECC memory includes a set of registers, wherein: each register corresponds to an ECC code word, each ECC code word corresponds to a section in the data memory, and each register stores a state of the section.
In some embodiments, at least one selected from the data memory and the ECC memory comprises magnetic random-access memory (MRAM).
In some embodiments, at least one selected from the data memory and the ECC memory include a memory unit cell including a magnetic tunnel junction (MTJ) having a property selected from reduced dimension, reduced coercive field, reduced magnetic anisotropy, and reduced saturation magnetization compared to a memory unit cell having a bit error rate between 10 â12 and 10 â2 .
In some embodiments, the MJT has two properties selected from reduced dimension, reduced coercive field, reduced magnetic anisotropy, and reduced saturation magnetization compared to a memory unit cell having a bit error rate between 10 â12 and 10 â2 .
In some embodiments, the data memory includes static random-access memory (SRAM), dynamic random-access memory (DRAM), or embedded DRAM (eDRAM).
In some embodiments, the data scrubbing circuit or a host is configured to determine whether the data memory is protected, and the ECC memory is configured to: in accordance with a determination that the data memory is protected, store ECC check-bits; and in accordance with a determination that the data memory is not protected, store computing data.
In some embodiments, the data memory and the ECC memory are included in different memory circuits.
In some embodiments, the data memory and the ECC memory are included in a same memory circuit.
In some embodiments, the memory system is electrically coupled to a host device.
In some embodiments, the data memory and the ECC memory include a memory unit cell including a MTJ having a size between 20 nm and 200 nm and a MOS transistor having a width-to-length ratio between 1 and 200.
In some embodiments, the data scrubbing circuit is configured to: receive a protect command for data; and in response to receiving the protect command, for each data word in the data to be protected: identify an address for a data code word associated with the data word; determine, based on the address, whether the data word is in a data memory; in response to determining that the data word is in the data memory, read the data word from the data memory; in response to determining that the data word is not in the data memory: receive the data word; and write the data word to the data memory; perform ECC encoding computation on the data word; generate the data code word based on the ECC encoding computation; write the data code word to the data memory at the address; generate ECC check bits based on the ECC encoding computation; and write the generated ECC check bits to a corresponding partition in the ECC memory.
In some embodiments, the data scrubbing circuit is configured to: receive a scrub data command; in response to receiving the scrub data command, for each data word to be scrubbed: identify: a starting address for a data code word, and a corresponding ECC memory partition; read a data word associated with the starting address from a data memory; read ECC check bits associated with the corresponding ECC memory partition from an ECC memory; perform ECC decoding computation based on the data word and ECC check bits; determine whether the data word includes an error based on the ECC decoding computation; in response to determining that the data word includes the error, replace error bits with correctable error bits in the data word, wherein the data word including the correctable error bits is a scrubbed data word; in response to determining that the data word does not include the error, forgo replacing the error bits with the correctable error bits in the data word, wherein the data word is the scrubbed data word; determine whether the scrubbed data word is requested by a host; in response to determining that the scrubbed data is requested by the host, output the scrubbed data word to a memory controller electrically coupled to the host; and in response to determining that the scrubbed data is not requested by the host, forgo outputting the scrubbed data word to the memory controller.
In some embodiments, a method of operating a memory system, the memory system comprising: a data memory; an ECC memory; and a data scrubbing circuit electrically coupled to the ECC memory and the data memory, the method comprises: in response to receiving a scrub data command, correcting, using the data scrubbing circuit, an error in the data memory.
In some embodiments, a code word length used to correct the error is longer than a word length used during normal access of the data memory.
In some embodiments, the data scrubbing circuit comprises a data buffer, a data scrubbing controller, an ECC encoding circuit, and an ECC decoding circuit.
In some embodiments, the method further comprises concurrently accessing the data memory while correcting the error in the data memory.
In some embodiments, the method further comprises detecting an environmental condition, using an environmental disturbance sensor; and generating the scrub data command based on the detected environmental condition.
In some embodiments, the environmental condition includes at least one of a temperature and a magnetic field.
In some embodiments, the method further comprises detecting change in known data; and generating the scrub data command based on the detection of the change.
In some embodiments, the method further comprises tracking a time lapsed; determining whether the time lapsed is greater than a timing threshold, and generating the scrub data command in accordance with the determination that the time lapsed is greater than the timing threshold.
In some embodiments, the ECC memory includes a plurality of partitions, and the data memory includes a plurality of ranges of memory addresses, each partition corresponding to a range of memory addresses in the data memory.
In some embodiments, the ECC memory includes a partition having a number of ECC bits associated with a data scrubbing algorithm, the method further comprising performing an ECC encoding method using the number of ECC bits.
In some embodiments, the ECC memory includes a set of registers, wherein: each register corresponds to an ECC code word, each ECC code word corresponds to a section in the data memory, and each register stores a state of the section.
In some embodiments, at least one selected from the data memory and the ECC memory comprises magnetic random-access memory (MRAM).
In some embodiments, at least one selected from the data memory and the ECC memory include a memory unit cell including a magnetic tunnel junction (MTJ) having a property selected from reduced dimension, reduced coercive field, reduced magnetic anisotropy, and reduced saturation magnetization compared to a memory unit cell having a bit error rate between 10 â12 and 10 â2 .
In some embodiments, the MJT has two properties selected from reduced dimension, reduced coercive field, reduced magnetic anisotropy, and reduced saturation magnetization compared to a memory unit cell having a bit error rate between 10 â12 and 10 â2 .
In some embodiments, the data memory includes static random-access memory (SRAM), dynamic random-access memory (DRAM), or embedded DRAM (eDRAM).
In some embodiments, the method further comprises determining whether the data memory is protected; in accordance with a determination that the data memory is protected, storing ECC check-bits in the ECC memory; and in accordance with a determination that the data memory is not protected, store computing data in the ECC memory.
In some embodiments, the data memory and the ECC memory are included in different memory circuits.
In some embodiments, the data memory and the ECC memory are included in a same memory circuit.
In some embodiments, the memory system is electrically coupled to a host device.
In some embodiments, the data memory and the ECC memory include a memory unit cell including a MTJ having a size between 20 nm and 200 nm and a MOS transistor having a width-to-length ratio between 1 and 200.
In some embodiments, the method further comprises receiving a protect command for data; and in response to receiving the protect command, for each data word in the data to be protected: identifying an address for a data code word associated with the data word; determining, based on the address, whether the data word is in a data memory; in response to determining that the data word is in the data memory, reading the data word from the data memory; in response to determining that the data word is not in the data memory: receiving the data word from; and writing the data word to the data memory; performing ECC encoding computation on the data word; generating the data code word based on the ECC encoding computation; writing the data code word to the data memory at the address; generating ECC check bits based on the ECC encoding computation; and writing the generated ECC check bits to a corresponding partition in an ECC memory.
In some embodiments, the method further comprises in response to receiving the scrub data command, for each data word to be scrubbed: identifying: a starting address for a data code word, and a corresponding ECC memory partition; reading a data word associated with the starting address from a data memory; reading ECC check bits associated with the corresponding ECC memory partition from an ECC memory; performing ECC decoding computation based on the data word and ECC check bits; determining whether the data word includes an error based on the ECC decoding computation; in response to determining that the data word includes the error, replacing error bits with correctable error bits in the data word, wherein the data word including the correctable error bits is a scrubbed data word; in response to determining that the data word does not include the error, forgoing replacing the error bits with the correctable error bits in the data word, wherein the data word is the scrubbed data word; determining whether the scrubbed data word is requested by a host; in response to determining that the scrubbed data is requested by the host, outputting the scrubbed data word to a memory controller electrically coupled to the host; and in response to determining that the scrubbed data is not requested by the host, forgoing outputting the scrubbed data word to the memory controller.
In some embodiments, the memory system is included in one selected from an edge-AI system, a neural-network system in data centers, an internet-of-things system, an automotive electronics system, microcontroller system, a mobile communication system, a programmable computing system, a hardware security system, a telematics system, a biomedical electronics device, a robot, and a drone.
In some embodiments, a memory system comprises: a first memory circuit associated with a first bit error rate; a second memory circuit associated with a second bit error rate, wherein the first bit error rate is greater than the second bit error rate; and a data word stored in the first and second memory circuits, wherein: the data word includes a first partition associated with the first bit error rate and a second partition associated with the second bit error rate, the first partition of the data word is stored in the first memory circuit, and the second partition of the data word is stored in the second memory circuit.
In some embodiments, the memory system further comprises a data scrubbing circuit electrically coupled to the first and second memory circuits, wherein: the data scrubbing circuit controls the first memory circuit to reduce the first error rate to a third error rate, the data scrubbing circuit controls the second memory circuit to reduce the second error rate to a fourth error rate, and the reduction of the first bit error rate is greater than the reduction of the second bit error rate.
In some embodiments, the first memory circuit includes a first memory unit cell including a first magnetic tunnel junction (MTJ) having a first size and a first MOS transistor having a first channel width to channel length (W/L) ratio, the second memory circuit includes a second memory unit cell including a second MTJ having a second size and a second MOS transistor having a second W/L ratio, the first size is larger than the second size, and the first W/L ratio is larger than the second W/L ratio.
In some embodiments, the first memory circuit includes a memory unit cell including a MTJ having a size between 40 nm and 200 nm and a MOS transistor having a W/L ratio between 2 and 200.
In some embodiments, the second memory circuit includes a memory unit cell including a MTJ having a size between 20 nm and 100 nm and a MOS transistor having a W/L ratio between 1 and 100.
In some embodiments, the first memory circuit uses a first read voltage, a first sensing time, and a first word-line (WL) voltage, the second memory circuit uses a second read voltage, a second sensing time, and a second WL voltage, the first read voltage is greater than the second read voltage, the first sensing time is greater than the second sensing time, and the first WL voltage is greater than the second WL voltage.
In some embodiments, the first memory circuit uses a first write voltage, a first write time, and a first WL voltage, the second memory circuit uses a second write voltage, a second write time, and a second WL voltage, the first write voltage is greater than the second write voltage, the first write time is greater than the write sensing time, and the first WL voltage is greater than the second WL voltage.
In some embodiments, in a floating point format, the first partition includes a sign bit, exponent bits, and higher order part of mantissa bits.
In some embodiments, in an integer format, the first partition includes a sign bit and higher order bits.
In some embodiments, in a floating point format, the second partition includes a lower order part of mantissa bits.
In some embodiments, in an integer format, the second partition includes lower order bits.
In some embodiments, a method of operating a memory system, the memory system comprising a first memory circuit and a second memory circuit, the method comprises: determining a first partition of a data word to be stored in the memory system based on a first bit error rate; determining a second partition of the data word to be stored in the memory system based on a second bit error rate, the first bit error rate greater than the second bit error rate; storing the first partition of a data word in a first memory circuit; and storing the second partition of a data word in a second memory circuit, wherein: the first memory circuit is associated with the first bit error rate, and the second memory circuit is associated with the second bit error rate.
In some embodiments, the method further comprises controlling the first memory circuit to reduce the first error rate to a third error rate; and controlling the second memory circuit to reduce the second error rate to a fourth error rate, wherein the reduction of the first bit error rate is greater than the reduction of the second bit error rate.
In some embodiments, the first memory circuit includes a first memory unit cell including a first MTJ having a first size and a first MOS transistor having a first channel W/L ratio, the second memory circuit includes a second memory unit cell including a second MTJ having a second size and a second MOS transistor having a second W/L ratio, the first size is larger than the second size, and the first W/L ratio is larger than the second W/L ratio.
In some embodiments, the first memory circuit includes a memory unit cell including a MTJ having a size between 40 nm and 200 nm and a MOS transistor having a W/L ratio between 2 and 200.
In some embodiments, the second memory circuit includes a memory unit cell including a MTJ having a size between 20 nm and 100 nm and a MOS transistor having a W/L ratio between 1 and 100.
In some embodiments, the method further comprises using, in the first memory circuit, a first read voltage, a first sensing time, and a first WL voltage; and using, in the second memory circuit, a second read voltage, a second sensing time, and a second WL voltage, wherein: the first read voltage is greater than the second read voltage, the first sensing time is greater than the second sensing time, and the first WL voltage is greater than the second WL voltage.
In some embodiments, the method further comprises using, in the first memory circuit, a first write voltage, a first write time, and a first WL voltage; and using, in the second memory circuit, a second write voltage, a second write time, and a second WL voltage, wherein: the first write voltage is greater than the second write voltage, the first write time is greater than the write sensing time, and the first WL voltage is greater than the second WL voltage.
In some embodiments, in a floating point format, the first partition includes a sign bit, exponent bits, and higher order part of mantissa bits.
In some embodiments, in an integer format, the first partition includes a sign bit and higher order bits.
In some embodiments, in a floating point format, the second partition includes a lower order part of mantissa bits.
In some embodiments, in an integer format, the second partition includes lower order bits.
In some embodiments, the memory system is included in one selected from an edge-AI system, a neural-network system in data centers, an internet-of-things system, an automotive electronics system, microcontroller system, a mobile communication system, a programmable computing system, a hardware security system, a telematics system, a biomedical electronics device, a robot, and a drone.
In some embodiments, a memory system comprises: a data input; a multi-level cell (MLC) array; a write circuit electrically coupled to the MLC array and the data input; a Gray code-to-binary decoder circuit electrically coupled to the write circuit; a readout circuit electrically coupled to the MLC array; a binary-to Gray code encoder circuit electrically coupled to the readout circuit and the data input; a memory circuit configured to store ECC check bits; an ECC encoder electrically coupled to the memory circuit and binary-to Gray code encoder circuit; an ECC decoder electrically coupled to the memory circuit and the Gray code-to-binary encoder circuit and configured to output recovered data; and a data scrubbing controller configured to control data recovery in the memory system.
In some embodiments, the MLC array comprises a memory cell circuit having greater than two stable physical states.
In some embodiments, the memory cell circuit is one selected from floating gate FLASH cell organized as a NOR cell, floating gate FLASH cell organized as a NAND cell, charge-trapping FLASH cells organized as a NOR cell, charge-trapping FLASH cells organized as a NAND cell, phase-change memory (PCM) cell, and resistive-memory (RRAM) cell.
In some embodiments, the ECC encoder and decoder use in one selected from Hamming code, BCH code, Reed-Solomon code, and LDPC code.
In some embodiments, the memory circuit is located on a different integrated circuit than the MLC array.
In some embodiments, the memory circuit is located in a predetermined partition of the MLC array.
In some embodiments, the data scrubbing controller is configured to initiate a data scrubbing operation at predetermined intervals, in response to a detection of an environmental disturbance, or in response to receiving a command from a host.
In some embodiments, a method of data-scrubbing a MLC comprises: reading data from the MLC, the data represented in binary code or an analog value; converting the data to Gray code; reading corresponding check bit data from a memory circuit configured to store ECC check bits; computing a location of a correctable error in the data in Gray code; correcting the correctable error in the data in Gray code; converting the corrected data to binary code or a corrected analog value; and writing, with a write circuit, the corrected data over the data in the MLC.
In some embodiments, the MLC array comprises a memory cell circuit having greater than two stable physical states.
In some embodiments, the memory cell circuit is one selected from floating gate FLASH cell organized as a NOR cell, floating gate FLASH cell organized as a NAND cell, charge-trapping FLASH cells organized as a NOR cell, charge-trapping FLASH cells organized as a NAND cell, phase-change memory (PCM) cell, and resistive-memory (RRAM) cell.
In some embodiments, the method further comprises ECC encoding and decoding in one selected from Hamming code, BCH code, Reed-Solomon code, and LDPC code.
In some embodiments, the memory circuit is located on a different integrated circuit than the MLC array.
In some embodiments, the memory circuit is located in a predetermined partition of the MLC array.
In some embodiments, the method further comprises initiating a data scrubbing operation at predetermined intervals, in response to a detection of an environmental disturbance, or in response to receiving a command from a host.
In some embodiments, the memory system is included in one selected from an edge-AI system, a neural-network system in data centers, an internet-of-things system, an automotive electronics system, microcontroller system, a mobile communication system, a programmable computing system, a hardware security system, a telematics system, a biomedical electronics device, a robot, and a drone.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 illustrates a system including a memory system, in accordance with an embodiment.
FIG. 2 illustrates a data memory and an ECC memory, in accordance with an embodiment.
FIG. 3 illustrates a method of operating a memory system, in accordance with an embodiment.
FIG. 4 illustrates a method of operating a memory system, in accordance with an embodiment.
FIG. 5 illustrates a memory system, in accordance with an embodiment.
FIG. 6 illustrates a data word partition, in accordance with an embodiment.
FIG. 7 illustrates a method of operating a memory system, in accordance with an embodiment.
FIG. 8 illustrates a memory system, in accordance with an embodiment.
FIG. 9 illustrates data recovery, in accordance with an embodiment.
FIG. 10 illustrates a method of operating a memory system, in accordance with an embodiment.
FIG. 11 illustrates a system including a memory system, in accordance with an embodiment.
FIG. 12 illustrates an example of a computing device including a memory system, in accordance with an embodiment.
DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS
In the following description of embodiments, reference is made to the accompanying drawings which form a part hereof, and in which it is shown by way of illustration specific embodiments which can be practiced. It is to be understood that other embodiments can be used and structural changes can be made without departing from the scope of the disclosed embodiments.
FIG. 1 illustrates a memory system that includes a memory system 100 . In some embodiments, the memory system 100 is electrically coupled to a host 160 and a memory controller 170 . In some examples, the memory system 100 may include up to 1 GB of storage on a single die.
In some examples, the host 160 or the memory controller 170 may generate a scrub data command to initiate data scrubbing of data memory in the memory system 100 or generate a protect command to initiate protection of data memory in the memory system 100 . In some examples, conditions that initiate the generation of the scrub data command may be programmable by the host 160 or the memory controller 170 . In some examples, conditions that initiate the generation of the protect command may be programmable by the host 160 or the memory controller 170 .
As an exemplary advantage, the memory system 100 may achieve high error-correction and data-scrubbing efficiency. For example, exemplary embodiments of the memory system 100 may achieve two to four times power reduction without a substantial performance or area tradeoff, compared to memory systems that do not utilize the disclosed scrub data command, in response to specific conditions (e.g., a changing environment), as discussed below. Memory systems that do not utilize the disclosed scrub data command or the disclosed protect command may scrub or protect data when scrubbing or protection may not be necessary (e.g., the bit error rate sufficiently meets system requirements). Such memory systems may not be efficient (e.g., higher power consumption, reduced speed) because data is protected or scrubbed indiscriminately (e.g., only during power-up or power-down of a system). Due to the improved efficiency, in some examples, design requirements for MRAM using Spin-Transfer-Torque (STT) for write operations may be relaxed. As another example, data retention errors may be reduced using comparable MTJ manufacturing processes (e.g., device fabrication cost may be reduced). As yet another example, using the memory system 100 , a MRAM device may linearly shrink up to 70% due to the relaxed requirements.
As used herein, a âscrub data commandâ is a command configured to initiate data scrubbing operation of the data memory. The scrub data command is generated and transmitted to the data scrubbing circuit in accordance with a determination that specific conditions are met. Such specific conditions may include conditions identified during normal operations, such as environmental condition, time lapse, and changes in known data (such as herein described). The normal operations include but are not limited to read and write operations, row activate and precharge operations, refresh operations, sector program and erase operations, defect repair operations, and wear-leveling operations. When these specific conditions are not met, the scrub data command is not generated to avoid unnecessary data scrubbing. For example, in a conventional memory system, data may be automatically scrubbed during power-on or power-off of the system. In the disclosed memory system, the data may only be scrubbed in response to receiving a scrub data command; powering-on or powering-off may not sufficiently cause the scrub data command to be generated.
As used herein a âprotect commandâ is a command configured to initiate data protection of the data memory. The protect command is generated and transmitted to the data scrubbing circuit in accordance with a determination that specific conditions are met. When these specific conditions are not met, the protect command would not be generated to avoid unnecessary encoding. For example, in a conventional memory system, data may be protected by default. In the disclosed memory system, the data may only be protected in response to receiving a protect command.
For example, high performance MRAM included in memory system 100 may be efficiently protected or scrubbed and be more suitable for edge-AI (e.g., smart speaker, dash camera, drone, robot, autonomous vehicle) or neural-network applications, which require faster and more efficient memories (e.g., high bandwidth and low latency, high performance after model compression, high performance at high temperature, uninterrupted data access). Memory technologies that use non-deterministic physical process to program may suffer from high bit-error-rate (BER). Using the disclosed data scrubbing and protection methods, the memory system 100 may be advantageously enable more robust operations in a system such as an autonomous vehicle.
The memory system 100 may include a data scrubbing circuit 110 , data memory 120 , and an ECC memory 130 . In some embodiments, the data memory 120 is a random-access memory (RAM) of a computer system. In some embodiments, the data memory 120 and the ECC memory 130 are non-volatile RAM.
In some embodiments, the data scrubbing circuit 110 performs data scrubbing without affecting read or write access of data memory 120 . By performing data protection or data scrubbing concurrently with memory data access, memory errors (e.g., magnetic tunnel junction (MTJ) errors) may be reduced without adding latency in a critical path (e.g., scrubbing data at higher read and write speeds, scrubbing data without affecting nominal read and write speeds). For example, the reduced latency may allow the memory system to operate at TB/s bandwidth.
In some embodiments, the data scrubbing circuit 110 includes a pipelined ECC decoder circuit and local registers to track a current position within a code word associated with an ECC code. In some embodiments, the data memory 120 is divided into a plurality of sub-circuits, commonly referred to as a memory bank. Each memory bank can be configured to operate independently from other memory banks.
As an example, during a protection or data scrub operation, the memory system 100 may receive a data access command from a host (e.g., an edge-AI system). The data access command may be associated with an operation (e.g., read data, write data) on a data memory bank as the on-going data protect or data scrub operation is performed on a different memory bank. In this scenario, the on-going data protect or data scrub operation may proceed concurrently with the data access.
The data access command may be associated with an operation (e.g., read data, write data) on a data memory bank as the on-going data protect or data scrub operation is performed on the same memory bank. In this scenario, the data scrubbing controller 113 may pause the data protect or data scrub operation and release control of the data memory bank to the data access operation, such as a read operation or a write operation. After the data access operation is completed, the data scrubbing controller regains control of the data memory bank, and the paused data protect or data scrub operation resumes from the position at the ECC code word (e.g., at the corresponding address) prior to the interruption. In some examples, the data scrubbing controller 113 may perform data protect or data scrub operations on a different memory bank during this period.
In some examples, the data scrubbing circuit or the host (e.g., a central processing unit (CPU), a graphical processing unit (GPU), a system-on-a-chip (SoC), a programmable processor, an application special integrated circuit, or a microcontroller) is configured to determine whether the data memory is protected (e.g., the data scrubbing circuit or the host checks the registers in the ECC memory to see if a corresponding section is protected), and the ECC memory is configured to in accordance with a determination that the data memory is protected, store ECC check-bits and in accordance with a determination that the data memory is not protected, store computing data. For example, if the computing data in the data memory is not protected (e.g., ECC is not required), then the ECC memory may be used to store additional computing data. The data scrubbing circuit may be electrically coupled to the ECC memory and the data memory, as shown. As an exemplary advantage, a product may release data storage capacity of an ECC memory to a host system if no harsh environment is expected (e.g., a wearable electronic device that is not in a high temperature or high magnetic field environment).
In some examples, an ECC memory is configured to store computing data at a first time and in response to initiation of a protect command, the ECC memory is updated to store ECC check-bits. In these examples, the computing data may be moved to an empty area in the data memory, a different storage device in the system, or a remote storage device through data network. If none of these is possible, the memory system may send an error message to the host.
In some embodiments, the data memory and the ECC memory are included in different memory circuits. For example, the data memory and the ECC memory are included on different chips. In some embodiments, the data memory and the ECC memory are included in a same memory circuit. For example, the data memory and the ECC memory are included on a same chip. As another example, the data memory and the ECC memory are included in a same memory array; the data memory is included in a first portion of the array, and the ECC memory is included in a second portion of the array, for example.
By achieving the high error-correction and data-scrubbing efficiency benefits described herein, the memory unit cell can be configured to enhance rewrite endurance or performance, reduce power consumption, or a combination of these desirable traits. This may be achieved without reducing the error rate of the memory system (e.g., the high error-correction and data-scrubbing efficiencies of the disclosed system may at least offset the increased error rate associated with achieving these desirable traits).
For example, voltage levels of a write operation may be reduced by 5-50%, enhancing rewrite endurance of the memory cell and reducing power consumption without reducing the error rate of the memory system (e.g., sufficient write voltage or write time to mitigate device and circuit mismatches and/or stochastic STT effect without additional circuitry, reduced probability of breakdown during write operation). As another example, voltage levels of a read operation of the memory cell may be increased by 5-50% or a read time may be reduced by 5-50%, enhancing read performance without reducing the error rate of the memory system (e.g., sufficient read voltage or read time to mitigate device and circuit mismatches without additional circuitry, read disturb errors may be reduced). In some examples, read performance may improve to greater than 7 GB/s for a 1 MB array.
In some embodiments, the data memory may include magnetic random-access memory (MRAM). In some embodiments, the ECC memory may include MRAM. In some examples, at least one selected from the data memory and the ECC memory include a memory unit cell including a magnetic tunnel junction (MTJ) having at one property selected from reduced dimension, reduced coercive field, reduced magnetic anisotropy, and reduced saturation magnetization compared to a memory unit cell having a bit error rate between 10 â12 and 10 â2 . In some examples, the data memory and the ECC memory include a memory unit cell including a MTJ having a size between 20 nm and 200 nm and a MOS transistor having a width-to-length ratio between 1 and 200.
In some embodiments, the data memory may include static random-access memory (SRAM), dynamic random-access memory (DRAM), or embedded DRAM (eDRAM). In some embodiments, the ECC memory may include SRAM, DRAM, or eDRAM. For example, the SRAM, DRAM, or eDRAM may include memory unit cells implemented in submicron (e.g., 28 nanometers and below) technologies having a bit error rate between 10 â16 and 10 â10 . As such, the memory system 100 may advantageously allow scaling of SRAM, DRAM, or eDRAM technologies to smaller technology nodes without compromising power, area, or performance or soft error (e.g., read-disturb, write error, retention error) rates. Additionally, the SRAM, DRAM, or eDRAM at smaller technology nodes may be more radiation tolerant using the memory system 100 .
In some embodiments, the data scrubbing circuit is configured to, in response to receiving a scrub data command, correct an error in the data memory. Memory systems that do not utilize the disclosed scrub data command may scrub data when scrubbing may not be necessary (e.g., the bit error rate sufficiently meets system requirements (e.g., usable bit error rate (UBER)). Such memory systems may not be efficient (e.g., higher power consumption, reduced speed) because data is scrubbed indiscriminately. By including a data scrubbing circuit configured to correct an error in the data memory in response to receiving a scrub data command, data can be scrubbed efficiently without unnecessary scrubbing.
In some embodiments, a code word length used to correct the error is longer than a word length used during normal access of the data memory. For example, words during normal access are a part of an ECC code word, such that the words are ECC protected. That is, the entire ECC code word may not be used during normal read operation (e.g., the normal access word portions are accessed). There are many ways to handle the write operation. For example, a code word length may have a length of 8192 bits, and a non-encoded word may have a length of 64 bits.
In some embodiments, the data memory 120 is divided into a plurality of pages, each page having a size of an ECC code word length (e.g., 8192 bits). When a host (e.g., an edge-AI system) sends a write command with a data word (e.g., a word having a length of 64 bits), the data scrubbing controller 113 would mark a destination page of the data word as âunprotectedâ using an extra bit (e.g., a page marker bit) included in each page. When the data scrubbing controller 113 initiates a data scrub operation on an âunprotectedâ page, the ECC check bit data in the corresponding ECC memory 130 would not be used immediately. Instead, the data scrubbing controller would first perform a protect operation to generate a set of ECC check bits corresponding to the new page data, and update the page marker
CLAIMS
Claims ( 18 )
We claim:
1. A system, comprising:
one or more memories for storing data; and
one more circuits configured to perform a method comprising:
encoding a unit of data to generate a set of check bits, wherein:
the check bits are configured for error correction, and
the unit of data is longer than a word length used for normal access of the one or more memories;
writing the generated check bits to a corresponding partition in the one or more memories;
decoding the unit of data and the check bits;
identifying, via the decoded unit of data and the decoded check bits, an error in the unit of data; and
in response to identifying the error, correcting, via the decoded check bits, the identified error.
2. The system of claim 1 , wherein the method further comprises determining a bit error rate (BER) associated with the one or more memories, wherein the determining the BER comprises detecting change in known data.
3. The system of claim 2 , wherein the detecting the change in the known data comprises one or more of:
detecting a change in a number of 0s and 1s in the known data,
comparing the known data to all 0s and all 1s,
comparing the known data to a predetermined pattern, and
decoding the known data via an error correction code.
4. The system of claim 1 , wherein the method further comprises:
determining a BER associated with the one or more memories;
comparing the BER to a threshold BER; and
in accordance with a determination that the threshold bit error rate is reached, generating one or more signals, wherein the one or more signals are configured to:
change a data scrubbing frequency; and
initiate data scrubbing of the one or more memories.
5. The system of claim 1 , wherein the method further comprises:
receiving a second command for scrubbing the data;
in response to receiving the second command, for each data word to be scrubbed:
identifying:
a starting address for a data code word, and
the corresponding memory partition;
reading the data word associated with the starting address from the one or more memories;
reading the check bits associated with the corresponding memory partition;
performing decoding computation based on the data word and the check bits;
determining whether the data word includes an error based on the decoding computation;
in accordance with a determination that the data word includes the error, replacing error bits associated with the error with correctable error bits in the data word.
6. The system of claim 1 , wherein the one or more circuits comprise a processor.
7. The system of claim 1 , wherein the one or more memories comprise magnetic random-access memory (MRAM).
8. The system of claim 1 , wherein:
the one or more circuits comprise a data scrubbing circuit, and
the data scrubbing circuit is configured to perform the generating the check bits and the writing the generated check bits to the corresponding partition in the one or more memories.
9. The system of claim 1 , wherein:
the one or more memories comprises an ECC memory, and
the generated check bits are written to the corresponding partition in the ECC memory.
10. A method, comprising:
encoding a unit of data to generate a set of check bits, wherein:
the unit of data is stored in one or more memories,
the check bits are configured for error correction, and
the unit of data is longer than a word length used for normal access of the one or more memories;
writing the generated check bits to a corresponding partition in the one or more memories;
decoding the unit of data and the check bits;
identifying, via the decoded unit of data and the decoded check bits, an error in the unit of data; and
in response to identifying the error, correcting, via the decoded check bits, the identified error.
11. The method of claim 10 , further comprising determining a BER associated with the one or more memories, wherein the determining the BER comprises detecting change in known data.
12. The method of claim 11 , wherein the detecting the change in the known data comprises one or more of:
detecting a change in a number of 0s and 1s in the known data,
comparing the known data to all 0s and all 1s,
comparing the known data to a predetermined pattern, and
decoding the known data via an error correction code.
13. The method of claim 10 , further comprising:
determining a BER associated with the one or more memories;
comparing the BER to a threshold BER;
in accordance with a determination that the threshold bit error rate is reached, generating one or more signals;
changing, via the one or more signals a data scrubbing frequency; and
initiating, via the one or more signals, data scrubbing of the one or more memories.
14. The method of claim 10 , further comprising:
receiving a second command for scrubbing the data;
in response to receiving the second command, for each data word to be scrubbed:
identifying:
a starting address for a data code word, and
the corresponding memory partition;
reading the data word associated with the starting address from the one or more memories;
reading the check bits associated with the corresponding memory partition;
performing decoding computation based on the data word and the check bits;
determining whether the data word includes an error based on the decoding computation;
in accordance with a determination that the data word includes the error, replacing error bits associated with the error with correctable error bits in the data word.
15. The method of claim 10 , wherein the method is performed by one or more circuits comprising a processor.
16. The method of claim 10 , wherein the one or more memories comprise magnetic random-access memory (MRAM).
17. The method of claim 10 , wherein a data scrubbing circuit is configured to perform the generating the check bits and the writing the generated check bits to the corresponding partition in the one or more memories.
18. The method of claim 10 , wherein:
the one or more memories comprises an ECC memory, and
the generated check bits are written to the corresponding partition in the ECC memory.
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