ABSTRACT
Abstract
The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate and an epitaxial stack disposed above the semiconductor substrate. The epitaxial stack includes first and second type epitaxial layers, the first and second type epitaxial layers having different material compositions. The first and second type epitaxial layers are alternatingly disposed in a vertical direction. The semiconductor device also includes a first doped region in the epitaxial stack and a second doped region in the epitaxial stack. The first doped region has a first dopant of a first conductivity type. The second doped region has a second dopant of a second conductivity type opposite the first conductivity type. The semiconductor device also includes first and second gate stacks disposed above the epitaxial stack. A portion of the first doped region and a portion of the second doped region are between the first and second gate stacks.
Description
PRIORITY
This is a continuation application of U.S. patent application Ser. No. 18/305,556, filed Apr. 24, 2023, which is a continuation application of U.S. patent application Ser. No. 17/224,671, filed Apr. 7, 2021, now issued as U.S. Pat. No. 11,637,099, which claims the benefits to U.S. Provisional Application Ser. No. 63/039,293, filed Jun. 15, 2020, each of which is incorporated herein by reference in its entirety.
BACKGROUND
The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs.
For example, as IC technologies progress towards smaller technology nodes, multi-gate devices have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short-channel effects (SCEs). A multi-gate device generally refers to a device having a gate structure, or portion thereof, disposed over more than one side of a channel region. Gate-all-around (GAA) transistors are examples of multi-gate devices that have become popular and promising candidates for high-performance and low-leakage applications. GAA transistors get their name from the gate structure which can extend around the channel region providing access to the stacked semiconductor channel layers on four sides. Compared to planar transistors, such configuration provides better control of the channel and drastically reduces SCEs (in particular, by reducing sub-threshold leakage).
An IC includes semiconductor devices that serve different functions, such as core functions and electrostatic discharging (ESD) functions. These different functions require semiconductor devices to have different constructions. At the same time, it is advantageous to have similar processes and similar process windows to fabricate these different semiconductor devices to reduce cost and improve yield. Although existing multi-gate (e.g., GAA) transistors and processes are generally adequate for their intended purposes, they have not been entirely satisfactory in every aspect. For example, in the course of IC evolution, backside power rails in addition to frontside interconnects have been introduced to increase the number of metal tracks available for greater power driving capability and simplified metal routing. How to form ESD devices (e.g., ESD diodes) compatible with multi-gate processes that also support backside power rail formation is a challenge faced by the semiconductor industry. The present disclosure aims to solve the above issues and other related issues.
BRIEF DESCRIPTION OF THE DRAWINGS
The present disclosure is best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
FIGS. 1 A, 1 B, and 1 C show a flow chart of a method of forming a semiconductor structure with ESD devices and backside power rails, according to various aspects of the present disclosure.
FIGS. 2 , 3 , and 4 illustrate perspective views of a portion of the semiconductor structure during fabrication processes according to the method of FIGS. 1 A- 1 C , in accordance with some embodiments of the present disclosure.
FIGS. 5 A, 5 B, 16 A, and 16 B illustrate top views of a portion of the semiconductor device during a fabrication process according to the method of FIGS. 1 A- 1 C , in accordance with some embodiments of the present disclosure.
FIGS. 6 A, 7 A, 8 A, 9 A, 10 A, 11 A, 12 A, 13 A, 14 A, 15 A, 17 A, 18 A, 19 A, 20 A, 21 A, 22 A, and 23 A illustrate cross-sectional views along the A-A line of a portion of the semiconductor device in FIG. 5 A during fabrication processes according to the method of FIGS. 1 A- 1 C , in accordance with some embodiments of the present disclosure.
FIGS. 6 B, 7 B, 8 B, 9 B, 10 B, 11 B, 12 B, 13 B, 14 B, 15 B, 17 B, 18 B, 19 B, 20 B, 21 B, 22 B, and 23 B illustrate cross-sectional views along the B-B line of a portion of the semiconductor device in FIG. 5 A during fabrication processes according to the method of FIGS. 1 A- 1 C , in accordance with some embodiments of the present disclosure.
DETAILED DESCRIPTION
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as âbeneath,â âbelow,â âlower,â âabove,â âupperâ and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Still further, when a number or a range of numbers is described with âabout,â âapproximate,â and the like, the term encompasses numbers that are within certain variations (such as +/â10% or other variations) of the number described, in accordance with the knowledge of the skilled in the art in view of the specific technology disclosed herein, unless otherwise specified. For example, the term âabout 5 nmâ may encompass the dimension range from 4.5 nm to 5.5 nm, 4.0 nm to 5.0 nm, etc.
This application generally relates to semiconductor structures and fabrication processes, and more particularly to an electrostatic discharge (ESD) protection device and methods of fabrication thereof that is compatible with multi-gate transistor process flow.
It is well known that extremely high voltages can develop in the vicinity of an integrated circuit (IC) due to the build-up of static charges. A high potential may be generated to an input or output buffer of the integrated circuit, which may be caused by a person touching a package pin that is in electrical contact with the input or output buffer. When the electrostatic charges are discharged, a high current is produced at the package nodes of the integrated circuit, and is referred to electrostatic discharge (ESD). ESD is a serious problem for semiconductor devices since it has the potential of destroying the entire integrated circuit. The duration of the ESD transient is very short, typically in the order of nanoseconds, and the conventional circuit breakers cannot react quickly enough to provide adequate protection. For this reason, it has become a known practice to incorporate ESD devices in ICs. In various embodiments, an IC may have multi-gate transistors (e.g., gate-all-around (GAA) transistors and/or FinFET transistors) placed in a core region providing core functions (e.g., logic and memory applications) and ESD devices placed in an ESD region providing ESD protection.
Yet a recent trend in IC evolution includes providing power rails (or power routings) on a back side (or backside) of a structure containing transistors in addition to an interconnect structure (which may include power rails as well) on a front side (or frontside) of the structure. This increases the number of metal tracks available in the structure for directly connecting to source/drain contacts and vias. It also increases the gate density for greater device integration than existing structures without the backside power rails. The backside power rails may have wider dimension than the first level metal (M0) tracks on the frontside of the structure, which beneficially reduces the power rail resistance. This approach, unfortunately, faces design and process issues. Particularly, a backside thinning process in removing bulk semiconductor substrate substantially eliminates current path for ESD devices comprising multiple fin elements. Accordingly, what is needed in the art is an ESD protection device whose formation process is compatible with the formation of multi-gate process flow while at the same time overcoming the deficiencies of the prior art.
The details of the structure and fabrication methods of the present disclosure are described below in conjunction with the accompanied drawings, which illustrate a process of making a GAA device in a core region and an ESD device in an ESD region, according to some embodiments. A GAA device refers to a device having vertically-stacked horizontally-oriented multi-channel transistors, such as nanowire transistors and nanosheet transistors. GAA devices are promising candidates to take CMOS to the next stage of the roadmap due to their better gate control ability, lower leakage current, and fully FinFET device layout compatibility. For the purposes of simplicity, the present disclosure uses GAA devices as an example. Those of ordinary skill in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures (such as FinFET devices) for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein.
Illustrated in FIGS. 1 A- 1 C is a method 100 of semiconductor fabrication including forming multi-gate transistors together with ESD devices (e.g., ESD diodes). The method 100 is merely an example, and is not intended to limit the present disclosure beyond what is explicitly recited in the claims. Additional operations can be provided before, during, and after the method 100 , and some operations described can be replaced, eliminated, or moved around for additional embodiments of the method. The method 100 is described below in conjunction with FIGS. 2 - 23 B . FIGS. 2 - 23 B have been simplified for the sake of clarity to better understand the inventive concepts of the present disclosure. FIGS. 2 - 4 illustrate perspective views of a semiconductor device (or device, or structure) 200 according to various stages of the method 100 . FIGS. 5 A, 5 B, 16 A, and 16 B illustrate top views of the device 200 according to various stages of the method 100 . FIGS. 6 A, 7 A, 8 A, 9 A, 10 A, 11 A, 12 A, 13 A, 14 A, 15 A, 17 A, 18 A, 19 A, 20 A, 21 A, 22 A , and 23 A illustrate cross-sectional views along the A-A line of a portion of the device 200 in FIG. 5 A which is in a channel region of a GAA transistor and along a lengthwise direction of the channel layers of the GAA transistor, according to various stages of the method 100 . FIGS. 6 B, 7 B, 8 B, 9 B, 10 B, 11 B, 12 B, 13 B, 14 B, 15 B, 17 B, 18 B, 19 B, 20 B, 21 B, 22 B, and 23 B illustrate cross-sectional views along the B-B line of a portion of the device 200 in FIG. 5 A which is along a lengthwise direction of a fin element (or fin) in an ESD device.
In some embodiments, the device 200 is a portion of an IC chip, a system on chip (SoC), or portion thereof, that includes various passive and active microelectronic devices such as resistors, capacitors, inductors, diodes, p-type field effect transistors (PFETs), n-type field effect transistors (NFETs), FinFET, nanosheet FETs, nanowire FETs, other types of multi-gate FETs, metal-oxide semiconductor field effect transistors (MOSFETs), complementary metal-oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high voltage transistors, high frequency transistors, memory devices, other suitable components, or combinations thereof. Additional features can be added in the device 200 , and some of the features described below can be replaced, modified, or eliminated in other embodiments of the device 200 .
The method 100 at operation 102 ( FIG. 1 A ) provides (or is provided with) the device 200 . Referring to <figref idrefs
PRIORITY
This is a continuation application of U.S. patent application Ser. No. 18/305,556, filed Apr. 24, 2023, which is a continuation application of U.S. patent application Ser. No. 17/224,671, filed Apr. 7, 2021, now issued as U.S. Pat. No. 11,637,099, which claims the benefits to U.S. Provisional Application Ser. No. 63/039,293, filed Jun. 15, 2020, each of which is incorporated herein by reference in its entirety.
BACKGROUND
The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs.
For example, as IC technologies progress towards smaller technology nodes, multi-gate devices have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short-channel effects (SCEs). A multi-gate device generally refers to a device having a gate structure, or portion thereof, disposed over more than one side of a channel region. Gate-all-around (GAA) transistors are examples of multi-gate devices that have become popular and promising candidates for high-performance and low-leakage applications. GAA transistors get their name from the gate structure which can extend around the channel region providing access to the stacked semiconductor channel layers on four sides. Compared to planar transistors, such configuration provides better control of the channel and drastically reduces SCEs (in particular, by reducing sub-threshold leakage).
An IC includes semiconductor devices that serve different functions, such as core functions and electrostatic discharging (ESD) functions. These different functions require semiconductor devices to have different constructions. At the same time, it is advantageous to have similar processes and similar process windows to fabricate these different semiconductor devices to reduce cost and improve yield. Although existing multi-gate (e.g., GAA) transistors and processes are generally adequate for their intended purposes, they have not been entirely satisfactory in every aspect. For example, in the course of IC evolution, backside power rails in addition to frontside interconnects have been introduced to increase the number of metal tracks available for greater power driving capability and simplified metal routing. How to form ESD devices (e.g., ESD diodes) compatible with multi-gate processes that also support backside power rail formation is a challenge faced by the semiconductor industry. The present disclosure aims to solve the above issues and other related issues.
BRIEF DESCRIPTION OF THE DRAWINGS
The present disclosure is best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
FIGS. 1 A, 1 B, and 1 C show a flow chart of a method of forming a semiconductor structure with ESD devices and backside power rails, according to various aspects of the present disclosure.
FIGS. 2 , 3 , and 4 illustrate perspective views of a portion of the semiconductor structure during fabrication processes according to the method of FIGS. 1 A- 1 C , in accordance with some embodiments of the present disclosure.
FIGS. 5 A, 5 B, 16 A, and 16 B illustrate top views of a portion of the semiconductor device during a fabrication process according to the method of FIGS. 1 A- 1 C , in accordance with some embodiments of the present disclosure.
FIGS. 6 A, 7 A, 8 A, 9 A, 10 A, 11 A, 12 A, 13 A, 14 A, 15 A, 17 A, 18 A, 19 A, 20 A, 21 A, 22 A, and 23 A illustrate cross-sectional views along the A-A line of a portion of the semiconductor device in FIG. 5 A during fabrication processes according to the method of FIGS. 1 A- 1 C , in accordance with some embodiments of the present disclosure.
FIGS. 6 B, 7 B, 8 B, 9 B, 10 B, 11 B, 12 B, 13 B, 14 B, 15 B, 17 B, 18 B, 19 B, 20 B, 21 B, 22 B, and 23 B illustrate cross-sectional views along the B-B line of a portion of the semiconductor device in FIG. 5 A during fabrication processes according to the method of FIGS. 1 A- 1 C , in accordance with some embodiments of the present disclosure.
DETAILED DESCRIPTION
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as âbeneath,â âbelow,â âlower,â âabove,â âupperâ and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Still further, when a number or a range of numbers is described with âabout,â âapproximate,â and the like, the term encompasses numbers that are within certain variations (such as +/â10% or other variations) of the number described, in accordance with the knowledge of the skilled in the art in view of the specific technology disclosed herein, unless otherwise specified. For example, the term âabout 5 nmâ may encompass the dimension range from 4.5 nm to 5.5 nm, 4.0 nm to 5.0 nm, etc.
This application generally relates to semiconductor structures and fabrication processes, and more particularly to an electrostatic discharge (ESD) protection device and methods of fabrication thereof that is compatible with multi-gate transistor process flow.
It is well known that extremely high voltages can develop in the vicinity of an integrated circuit (IC) due to the build-up of static charges. A high potential may be generated to an input or output buffer of the integrated circuit, which may be caused by a person touching a package pin that is in electrical contact with the input or output buffer. When the electrostatic charges are discharged, a high current is produced at the package nodes of the integrated circuit, and is referred to electrostatic discharge (ESD). ESD is a serious problem for semiconductor devices since it has the potential of destroying the entire integrated circuit. The duration of the ESD transient is very short, typically in the order of nanoseconds, and the conventional circuit breakers cannot react quickly enough to provide adequate protection. For this reason, it has become a known practice to incorporate ESD devices in ICs. In various embodiments, an IC may have multi-gate transistors (e.g., gate-all-around (GAA) transistors and/or FinFET transistors) placed in a core region providing core functions (e.g., logic and memory applications) and ESD devices placed in an ESD region providing ESD protection.
Yet a recent trend in IC evolution includes providing power rails (or power routings) on a back side (or backside) of a structure containing transistors in addition to an interconnect structure (which may include power rails as well) on a front side (or frontside) of the structure. This increases the number of metal tracks available in the structure for directly connecting to source/drain contacts and vias. It also increases the gate density for greater device integration than existing structures without the backside power rails. The backside power rails may have wider dimension than the first level metal (M0) tracks on the frontside of the structure, which beneficially reduces the power rail resistance. This approach, unfortunately, faces design and process issues. Particularly, a backside thinning process in removing bulk semiconductor substrate substantially eliminates current path for ESD devices comprising multiple fin elements. Accordingly, what is needed in the art is an ESD protection device whose formation process is compatible with the formation of multi-gate process flow while at the same time overcoming the deficiencies of the prior art.
The details of the structure and fabrication methods of the present disclosure are described below in conjunction with the accompanied drawings, which illustrate a process of making a GAA device in a core region and an ESD device in an ESD region, according to some embodiments. A GAA device refers to a device having vertically-stacked horizontally-oriented multi-channel transistors, such as nanowire transistors and nanosheet transistors. GAA devices are promising candidates to take CMOS to the next stage of the roadmap due to their better gate control ability, lower leakage current, and fully FinFET device layout compatibility. For the purposes of simplicity, the present disclosure uses GAA devices as an example. Those of ordinary skill in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures (such as FinFET devices) for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein.
Illustrated in FIGS. 1 A- 1 C is a method 100 of semiconductor fabrication including forming multi-gate transistors together with ESD devices (e.g., ESD diodes). The method 100 is merely an example, and is not intended to limit the present disclosure beyond what is explicitly recited in the claims. Additional operations can be provided before, during, and after the method 100 , and some operations described can be replaced, eliminated, or moved around for additional embodiments of the method. The method 100 is described below in conjunction with FIGS. 2 - 23 B . FIGS. 2 - 23 B have been simplified for the sake of clarity to better understand the inventive concepts of the present disclosure. FIGS. 2 - 4 illustrate perspective views of a semiconductor device (or device, or structure) 200 according to various stages of the method 100 . FIGS. 5 A, 5 B, 16 A, and 16 B illustrate top views of the device 200 according to various stages of the method 100 . FIGS. 6 A, 7 A, 8 A, 9 A, 10 A, 11 A, 12 A, 13 A, 14 A, 15 A, 17 A, 18 A, 19 A, 20 A, 21 A, 22 A , and 23 A illustrate cross-sectional views along the A-A line of a portion of the device 200 in FIG. 5 A which is in a channel region of a GAA transistor and along a lengthwise direction of the channel layers of the GAA transistor, according to various stages of the method 100 . FIGS. 6 B, 7 B, 8 B, 9 B, 10 B, 11 B, 12 B, 13 B, 14 B, 15 B, 17 B, 18 B, 19 B, 20 B, 21 B, 22 B, and 23 B illustrate cross-sectional views along the B-B line of a portion of the device 200 in FIG. 5 A which is along a lengthwise direction of a fin element (or fin) in an ESD device.
In some embodiments, the device 200 is a portion of an IC chip, a system on chip (SoC), or portion thereof, that includes various passive and active microelectronic devices such as resistors, capacitors, inductors, diodes, p-type field effect transistors (PFETs), n-type field effect transistors (NFETs), FinFET, nanosheet FETs, nanowire FETs, other types of multi-gate FETs, metal-oxide semiconductor field effect transistors (MOSFETs), complementary metal-oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high voltage transistors, high frequency transistors, memory devices, other suitable components, or combinations thereof. Additional features can be added in the device 200 , and some of the features described below can be replaced, modified, or eliminated in other embodiments of the device 200 .
The method 100 at operation 102 ( FIG. 1 A ) provides (or is provided with) the device 200 . Referring to FIG. 2 , the device 200 includes a region I for forming transistors and a region II for forming ESD devices. The transistors formed in the region I are for core applications such as for forming logic circuits, memory circuits, and other core circuits. The ESD devices, such as ESD diodes, formed in the region II are for protecting the device 200 from electrostatic discharging events. The device 200 includes a substrate 202 and an epitaxial stack 204 above the substrate 202 . Both the substrate 202 and the epitaxial stack 204 extend continuously from the region I to the region II. Further, a hard mask (HM) layer 212 is formed over the epitaxial stack 204 .
In some embodiments, the substrate 202 is a semiconductor substrate such as a silicon substrate. The substrate 202 may include various layers, including conductive or insulating layers formed on a semiconductor substrate. In the illustrated embodiment, the substrate 202 includes a dielectric capping layer 203 . In some embodiments, the dielectric capping layer 203 is an oxide layer. The dielectric capping layer 203 may be deposited using chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or oxidation. The dielectric capping layer 203 separates the substrate 202 into a top substrate portion 202 a and a bottom substrate portion 202 b . In some embodiments, the dielectric capping layer 203 serves as an etch stop or a chemical mechanical polishing (CMP) stop during a backside thinning process.
The substrate 202 may also include various doping configurations depending on design requirements as is known in the art. For example, different doping profiles (e.g., n-wells, p-wells) may be formed on the substrate 202 in regions designed for different device types (e.g., n-type field effect transistors (N-FET), p-type field effect transistors (P-FET)). The suitable doping may include ion implantation of dopants and/or diffusion processes. The substrate 202 may have isolation features (e.g., shallow trench isolation (STI) features) interposing the regions providing different device types. The substrate 202 may also include other semiconductors such as germanium, silicon carbide (SiC), silicon germanium (SiGe), or diamond. Alternatively, the substrate 202 may include a compound semiconductor and/or an alloy semiconductor. Further, the substrate 202 may optionally include an epitaxial layer (epi-layer), may be strained for performance enhancement, may include a silicon-on-insulator (SOI) structure, and/or may have other suitable enhancement features.
The epitaxial stack 204 includes epitaxial layers 206 of a first composition interposed by epitaxial layers 208 of a second composition. The first and second compositions can be different. The epitaxial layers 208 may include the same composition as the substrate 202 . In the illustrated embodiment, the epitaxial layers 206 are silicon germanium (SiGe) and the epitaxial layers 208 are silicon (Si). However, other embodiments are possible including those that provide for a first composition and a second composition having different oxidation rates and/or etch selectivity. For example, in some embodiments, either of the epitaxial layers
206 , 208 of the first composition or the second composition may include other materials such as germanium, a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide, an alloy semiconductor such as SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and/or GaInAsP, or combinations thereof. In some embodiments, the epitaxial layers
206 and 208 are substantially dopant-free (i.e., having an extrinsic dopant concentration from about 0 cm â3 to about 1Ã10 17 cm â3 ), where for example, no intentional doping is performed during the epitaxial growth process. By way of example, epitaxial growth of the epitaxial layers
206 , 208 of the first composition or the second composition may be performed by a molecular beam epitaxy (MBE) process, a metalorganic chemical vapor deposition (MOCVD) process, and/or other suitable epitaxial growth processes. In various embodiments, the substrate 202 is a crystalline substrate, the epitaxial layers
206 , 208 are crystalline semiconductor layers, and the epitaxial stack 204 is formed as a superlattice structure.
In some embodiments, each epitaxial layer 206 has a thickness ranging from about 2 nanometers (nm) to about 6 nm. The epitaxial layers 206 may be substantially uniform in thickness. Yet in the illustrated embodiment, the top epitaxial layer 206 is thinner (e.g., half the thickness) than other epitaxial layers 206 thereunder. In some embodiments, each epitaxial layer 208 has a thickness ranging from about 6 nm to about 12 nm. In some embodiments, the epitaxial layers 208 of the stack are substantially uniform in thickness. As described in more detail below, the epitaxial layers 208 or portions thereof may form channel layer(s) of the subsequently-formed GAA transistors in the region I and the thickness is chosen based on transistor performance considerations. The term channel layer(s) is used herein to designate any material portion for channel(s) in a transistor with nanoscale, or even microscale dimensions, and having an elongate shape, regardless of the cross-sectional shape of this portion. Thus, this term designates both circular and substantially circular cross-section elongate material portions, and beam or bar-shaped material portions including for example a cylindrical in shape or substantially rectangular cross-section. The epitaxial layers 206 in channel regions(s) may eventually be removed and serve to define a vertical distance between adjacent channel members for a subsequently-formed multi-gate device and the thickness is chosen based on device performance considerations. Accordingly, the epitaxial layers 206 may also be referred to as sacrificial layers, and epitaxial layers 208 may also be referred to as channel layers.
It is noted that three (3) layers of the epitaxial layers 206 and three (3) layers of the epitaxial layers 208 are alternately arranged as illustrated in FIG. 2 , which is for illustrative purposes only and not intended to be limiting beyond what is specifically recited in the claims. It can be appreciated that any number of epitaxial layers can be formed in the epitaxial stack 204 ; the number of layers depending on the desired number of channels layers for the device 200 . In some embodiments, the number of epitaxial layers 208 is between 2 and 10. It is also noted that while the epitaxial layers
206 , 208 are shown as having a particular stacking sequence, where an epitaxial layer 208 is the topmost layer of the epitaxial stack 204 , other configurations are possible. For example, in some cases, an epitaxial layer 206 may alternatively be the topmost layer of the epitaxial stack 204 . Stated another way, the order of growth for the epitaxial layers
206 , 208 , and thus their stacking sequence, may be switched or otherwise be different than what is shown in the figures, while remaining within the scope of the present disclosure.
In the illustrated embodiment, the hard mask (HM) layer 212 is formed over the epitaxial stack 204 prior to patterning in forming semiconductor fins. In some embodiments, the HM layer 212 includes an oxide layer 212 A (e.g., a pad oxide layer that may include SiO 2 ) and a nitride layer 212 B (e.g., a pad nitride layer that may include Si 3 N 4 ) formed over the oxide layer 212 A. The oxide layer 212 A may act as an adhesion layer between the epitaxial stack 204 and the nitride layer 212 B and may act as an etch stop layer for etching the nitride layer 212 B. In some examples, the HM layer 212 includes thermally grown oxide, CVD-deposited oxide, and/or ALD-deposited oxide. In some embodiments, the HM layer 212 includes a nitride layer deposited by CVD and/or other suitable technique.
The method 100 then proceeds to operation 104 ( FIG. 1 A ) where fin elements (or fins) 210 are formed by patterning the epitaxial stack 204 by using the patterned mask layer 212 . With reference to the example of FIG. 3 , in an embodiment of operation 104 , a plurality of fins 210 extending from the substrate 202 are formed extending lengthwise in the X direction, including fins 210 a in the region I and fins 210 b in the region II. In the illustrated embodiment, two fins 210 a are arranged in the Y direction in the region I and one fin 210 b is depicted in the region II. But the number of the fins
210 a or 210 b is not limited to and may be as small as one or three or more. In various embodiments, each of the fins 210 includes an upper portion constituted by the stacked epitaxial layers
206 and 208 , and a lower portion formed from the substrate 202 . The width W 1 of the upper portion of the fins 210 a in the region I along the Y direction is in a range from about 10 nm to about 40 nm in some embodiments. The width W 2 of the upper portion of the fins 210 b in the region II along the Y direction is wider than W 1 , such as in a range from about 50 nm to about 1000 nm in some embodiments. The length L 1 of the upper portion of the fins 210 a in the region I along the X direction and the length L 2 of the upper portion of the fins 210 b in the region II along the X direction may each range from about 90 nm to about 900 nm in some embodiments. In the region I, the fins 210 a may be designed for forming an NFET or a PFET. In the region II, the fins 210 b may be designed for forming an ESD diode. A large width W 2 of the fins 210 b provides lower ESD resistance and stronger ESD current conductivity.
The fins 210 may be fabricated using suitable processes including photolithography and etch processes. The photolithography process may include forming a photoresist layer (not shown) over the HM layer 212 , exposing the resist to a pattern, performing post-exposure bake processes, and developing the resist to form a masking element including the resist. In some embodiments, patterning the resist to form the masking element may be performed using an electron beam (e-beam) lithography process. The masking element may then be used to protect regions of the substrate 202 , and layers formed thereupon, while an etch process forms trenches 214 in unprotected regions through the HM layer 212 , through the epitaxial stack 204 , and into the substrate 202 , thereby leaving the plurality of extending fins 210 . The trenches 214 may be etched using dry etching, wet etching, RIE, and/or other suitable processes.
Numerous other embodiments of methods to form the semiconductor fins on the substrate may also be used including, for example, defining the fin region (e.g., by mask or isolation regions) and epitaxially growing the epitaxial stack 204 in the form of the fins 210 . In some embodiments, forming the fins 210 may include a trim process to decrease the width of the fins 210 . The trim process may include wet and/or dry etching processes. In some embodiments, the fins 210 may be fabricated using suitable processes including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers, or mandrels, may then be used to pattern the fins 210 by etching the epitaxial stack 204 and the substrate 202 . The etching process can include dry etching, wet etching, reactive ion etching (RIE), and/or other suitable processes.
At operation 106 , the method 100 ( FIG. 1 A ) forms isolation structures, such as shallow trench isolation (STI) features, between the fins 210 . Still referring to FIG. 3 , STI features 220 is disposed on the substrate 202 interposing the fins 210 . By way of example, in some embodiments, a dielectric layer is first deposited over the substrate 202 , filling the trenches 214 with dielectric material. In some embodiments, the dielectric layer may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric, combinations thereof, and/or other suitable materials. In various examples, the dielectric layer may be deposited by a CVD process, a SACVD process, a flowable CVD process, an ALD process, a PVD process, and/or other suitable process. In some embodiments, after deposition of the dielectric layer, the device 200 may be annealed, for example, to improve the quality of the dielectric layer. In some embodiments, the dielectric layer may include a multi-layer structure, for example, having one or more liner layers. In some embodiments of forming the STI features 220 , after deposition of the dielectric layer, the deposited dielectric material is thinned and planarized, for example by a chemical mechanical polishing (CMP) process, such that the upper surface of the topmost epitaxial layer 208 is exposed. Subsequently, the dielectric layer interposing the fins 210 are recessed. As shown in FIG. 3 , the STI features 220 are recessed providing the fins 210 extending above the STI features 220 . In some embodiments, the recessing process may include a dry etching process, a wet etching process, and/or a combination thereof. In some embodiments, a recessing depth is controlled (e.g., by controlling an etching time) so as to result in a desired height of the exposed upper portion of the fins 210 . In the illustrated embodiment, each of the layers of the epitaxial stack 204 is exposed. In furtherance of the embodiment, a top surface of the STI features 220 is recessed below a bottom surface of the epitaxial stack 204 .
The method 100 then proceeds to operation 108 ( FIG. 1 A ) where sacrificial layers/features are formed and in particular, dummy gate structures (or dummy gate stacks). While the present discussion is directed to a replacement gate (or gate-last) process whereby a dummy gate structure is formed and subsequently replaced, other configurations may be possible.
Referring to FIGS. 4 , 5 A -B, and 6 A-B, gate stacks 232 are formed. FIG. 4 is a perspective view of the device 200 , FIGS. 5 A and 5 B refer to top views of two embodiments of the device 200 , FIG. 6 A refers to a cross-sectional view in the region I taken in a fin 210 a and along the lengthwise direction of the fin 210 a (e.g., along the A-A line in FIG. 4 ), and FIG. 6 B refers to a cross-sectional view in the region II taken in the fin 210 b and along the lengthwise direction of the fin 210 b (e.g., along the B-B line in FIG. 4 ). The gate stacks 232 are oriented lengthwise along the Y direction. The gate stacks 232 have a width W 3 in a range from about 10 nm to about 100 nm and a length L 3 in a range from about 40 nm to about 950 nm, in some embodiments. In the region I, the length L 3 of the gate stacks 232 is larger than the width W 1 of the fins 210 a , and the gate stacks 232 engages the fins 210 from both the top surface and sidewalls of the fins 210 a . The portion of the fins 210 a underlying the dummy gate stacks 232 may be referred to as the channel region. The dummy gate stacks 232 may also define source/drain (S/D) regions of the fins 210 a , for example, the regions of the fins 210 a adjacent and on opposing sides of the channel region. A distance D 1 between adjacent gate stacks 232 may range from about 30 nm to about 200 nm. In the region II, the length L 3 of the gate stacks 232 is smaller than the width W 2 of the fin 210 b , and the gate stacks 232 are deposited above the top surface of the fin 210 b but not on its sidewalls ( FIG. 5 A ). A distance D 2 between two adjacent gate stacks 232 in the region II is in a range from about 110 nm to about 1020 nm, which is larger than D 1 , in some embodiments. In some embodiments, a ratio of D 2 /L 2 is not less than about 0.7. If the ratio of D 2 /L 2 is less than 70%, the relative close distance between two adjacent gate stacks 232 may introduce unwanted stray capacitance and degrade ESD performance. In furtherance of some embodiments, the ratio of D 2 /L 2 is larger than 1, which is that the distance D 2 being larger than the length L 2 of the fin 210 b and the gate stacks 232 being deposited on the STI features 220 that surrounds the fin 210 b ( FIG. 5 B ). A gap G 1 between two opposing edges of the gate stacks 232 and the fin 210 b may range from about 10 nm to about 60 nm.
In various embodiments, the gate stacks 232 are a dummy (sacrificial) gate stacks that are subsequently removed. Thus, in some embodiments using a gate-last process, the gate stacks 232 are dummy gate stacks and will be replaced by the final gate stack at a subsequent processing stage of the device 200 . In particular, the dummy gate stacks 232 may be replaced at a later processing stage by a high-K dielectric layer (HK) and metal gate electrode (MG) as will be discussed in more detail below.
In some embodiments, the dummy gate stack 232 includes a dummy dielectric layer 234
CLAIMS
Claims ( 20 )
What is claimed is:
1. A semiconductor device, comprising:
a semiconductor substrate;
an epitaxial stack disposed above the semiconductor substrate, the epitaxial stack including first and second type epitaxial layers, the first and second type epitaxial layers having different material compositions, and the first and second type epitaxial layers being alternatingly disposed in a vertical direction;
a first doped region in the epitaxial stack, the first doped region having a first dopant of a first conductivity type;
a second doped region in the epitaxial stack, the second doped region having a second dopant of a second conductivity type opposite the first conductivity type; and
first and second gate stacks disposed above the epitaxial stack,
wherein a portion of the first doped region and a portion of the second doped region are between the first and second gate stacks.
2. The semiconductor device of claim 1 , wherein the epitaxial stack includes an undoped region between the first doped region and the second doped region.
3. The semiconductor device of claim 1 , wherein at least one of the first and second doped regions has a bottom surface below a bottom surface of the epitaxial stack.
4. The semiconductor device of claim 1 , wherein:
the first doped region has a first edge facing the second doped region and a second edge facing away from the second doped region,
the second doped region has a third edge facing the first doped region and a fourth edge facing away from the first doped region, and
the first edge and the third edge are between the first and second gate stacks.
5. The semiconductor device of claim 4 , wherein the second edge and the fourth edge are between the first and second gate stacks.
6. The semiconductor device of claim 1 , wherein in a top view of the semiconductor device the first and second gate stacks are fully within a contour of a top surface of the epitaxial stack.
7. The semiconductor device of claim 1 , further comprising:
a first contact disposed on and in electrical coupling with the first doped region; and
a second contact disposed on and in electrical coupling with the second doped region,
wherein the first contact and the second contact are between the first and second gate stacks.
8. The semiconductor device of claim 7 , wherein the first contact, the second contact, the first gate stack, and the second gate stack each extend lengthwise in a same direction.
9. The semiconductor device of claim 1 , wherein the first type epitaxial layers include silicon, and the second type epitaxial layers include silicon germanium.
10. The semiconductor device of claim 1 , further comprising:
a frontside multilayer interconnect structure disposed above the epitaxial stack; and
a backside multilayer interconnect structure disposed under the semiconductor substrate.
11. A semiconductor device, comprising:
a stack of first semiconductor layers and second semiconductor layers alternatingly disposed in a vertical direction, the first semiconductor layers having a first material composition and the second semiconductor layers having a second material composition different from the first material composition;
a first doped region in the stack, the first doped region having a first dopant of a first conductivity type;
a second doped region in the stack, the second doped region having a second dopant of a second conductivity type opposite the first conductivity type;
a first contact disposed on and in electrical coupling with the first doped region;
a second contact disposed on and in electrical coupling with the second doped region;
a frontside multilayer interconnect structure disposed above the stack; and
a backside multilayer interconnect structure disposed under the stack, wherein the first contact is in electrical coupling with the frontside multilayer interconnect structure.
12. The semiconductor device of claim 11 , wherein the second contact is in electrical coupling with the frontside multilayer interconnect structure.
13. The semiconductor device of claim 11 , wherein the second contact is in electrical coupling with the backside multilayer interconnect structure.
14. The semiconductor device of claim 11 , further comprising:
a semiconductor substrate between the stack and the backside multilayer interconnect structure.
15. The semiconductor device of claim 14 , wherein at least one of the first and second doped regions extends downwardly into a top portion of the semiconductor substrate.
16. The semiconductor device of claim 11 , further comprising:
a first metal gate structure disposed above the stack; and
a second metal gate structure disposed above the stack,
wherein at least a portion of the first doped region and a portion of the second doped region is between the first and second metal gate structures.
17. A method of manufacturing a semiconductor device, comprising:
providing a structure having a substrate and a stack protruding from the substrate, the stack having first semiconductor layers and second semiconductor layers alternatingly arranged in a vertical direction, the first and second semiconductor layers having different material compositions;
depositing an isolation feature on sidewalls of the stack;
implanting a first dopant into a first region of the stack, the first dopant having a first conductivity type;
implanting a second dopant into a second region of the stack, the second dopant having a second conductivity type opposite the first conductivity type; and
forming a first metal gate structure above the first region;
forming a second metal gate structure above the second region, wherein at least a portion of the first region and a portion of the second region are between the first and second metal gate structures;
depositing a dielectric layer between the first and second metal gate structures;
forming a first contact through the dielectric layer and landing on the first region; and
forming a second contact through the dielectric layer and landing on the second region.
18. The method of claim 17 , wherein the second region is spaced apart from the first region.
19. The method of claim 17 , wherein in a top view of the semiconductor device the first and second metal gate structures are fully within a contour of a top surface of the stack.
20. The method of claim 17 , wherein in a top view of the semiconductor device the first and second metal gate structures are disposed on the isolation feature and outside of a contour of a top surface of the stack.
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