ABSTRACT
Abstract
A microchip including an outer chamber, compartment, or bladder; an inner chamber, compartment, or bladder inside said outer chamber, compartment, or bladder; an internal sipe separating at least a part of said inner and outer chambers, compartments, or bladders, and a Faraday cage. The microchip is configured to connect to a network of computers and includes an internal hardware firewall configured to deny access a protected portion of the microchip from the network. The sipe is formed by at least a portion of both an inner surface of the outer chamber, compartment, or bladder and an outer surface of the inner chamber, compartment, or bladder. The surface portions forming the sipe oppose each other and can move relative to each other in a sliding motion. At least a portion of an outer surface of the outer chamber, compartment, or bladder is proximate to an outer surface of the microchip.
Description
This application is a continuation of U.S. patent application Ser. No. 13/931,080 filed Jun. 28, 2013; which is a continuation of Ser. No. 13/769,292, filed Feb. 16, 2013, now abandoned; which is a continuation of U.S. patent application Ser. No. 12/292,769, filed Nov. 25, 2008, now U.S. Pat. No. 8,125,796, which is a continuation-in-part of U.S. patent application Ser. No. 12/292,553, filed Nov. 20, 2008, now U.S. Pat. No. 8,164,170, which is a non-provisional of U.S. Provisional Application No. 60/996,530, filed on Nov. 21, 2007, and U.S. Provisional Application No. 60/996,553, filed on Nov. 26, 2007. U.S. patent application Ser. No. 12/292,769, filed Nov. 25, 2008, is also a non-provisional of U.S. Provisional Application No. 60/996,553, filed on Nov. 26, 2007. The contents of all of the above-mentioned applications are hereby incorporated herein by reference.
BACKGROUND
1. Field of the Disclosure
The disclosure relates to a Faraday Cage surrounding semiconductor microchips, photovoltaic cells, and/or other micro and/or nano devices combined with the applicant's prior internal sipe inventions, including at least one compartment surrounded by at least one internal sipe, such as a slit. More specifically, a Faraday Cage coincides with an outer compartment, which forms one surface of a sipe surrounding an inner compartment including a personal computer microchip and/or a photovoltaic cell and/or a fuel cell and/or a battery.
The disclosure also relates to a semiconductor wafer, such as silicon, containing a multitude of microchips, such as with one or more core microprocessors. Instead of separating the microchips into separate dies in the conventional process, the entire semiconductor wafer is used essentially intact as a computer. More specifically, interconnects can be added to the printed circuit architecture of the wafer to connect the wafer microchips to other wafer microchips and/or other components on the wafer or external to it. Still more specifically, each microchip can be a complete system on a chip (SoC). Even more specifically, the semiconductor wafer can be used with other conventional interface devices for power and data, including wireless such as radio and/or optic, and/or wired such as fiber optic and/or electric, including for each SoC microchip on the wafer. In another specific embodiment, two or more semiconductor wafers can be stacked in vertical layers; for example, with a first wafer including microprocessors or cores; a second wafer including random access memory or RAM; and a third wafer including other components; each SoC microchip, in this example, can have one or more components on each of the three wafers.
The disclosure also relates to the semiconductor wafer including one or more of the applicant's prior internal sipe inventions, with an outer compartment having an internal sipe.
The disclosure also relates to the semiconductor wafer being surrounded by one or more Faraday Cages integrated into the internal sipe invention.
2. Brief Description of the Prior Art
Faraday Cage surrounding semiconductor microchips, photovoltaic cells, and/or other micro and/or nano devices, are described by the applicant in his U.S. application Ser. No. 10/802,049 filed Mar. 17, 2004, and published as Pub. No. US 2004/0215931 A1 on Oct. 28, 2004.
The applicant's prior internal footwear sipe inventions, including at least one compartment surrounded by at least one internal sipe, such as a slit, are described by the applicant in his U.S. patent application Ser. No. 11/802,930, filed May 25, 2007 and published as Pub. No. US 2008/0086916 A1 on Apr. 17, 2008, as well as in several earlier U.S. applications filed by the applicant.
Existing semiconductor wafers, currently up to 300 mm in diameter, are always cut into a large number of separate dies, with one microchip formed into a package from each flaw-free die cut from the semiconductor wafer; some dies are inherently defective and are discarded. A typical semiconductor wafer is shown in the applicant's U.S. application Ser. No. 10/684,657 filed Oct. 15, 2003.
As described in Wikipedia, âwafer scale integrationâ (WSI) is a yet-unused system of building very-large integrated circuit networks that use an entire silicon wafer to produce a single âsuper-chip.â Through a combination of large size and reduced packaging, WSI could lead to dramatically reduced costs for some systems, notably massively parallel supercomputers.
Many companies including TI and ITT attempted to develop âwafer scale integrationâ (WSI) production systems in the 1970's and '80's, but all failed and no products were released. Further attempts at WSI appear to be largely abandoned for decades.
One critical problem that has not been overcome is that of inherent flaws in semiconductor wafers. It has been an ongoing goal to develop methods to handle faulty areas of the wafers through logic, as opposed to sawing them out of the wafer. Generally, this approach uses a grid pattern of sub-circuits and ârewiresâ around the damaged areas using appropriate logic.
The overwhelming difficulty of this approach is illustrated by the history of famous computer pioneer Gene Amdahl, who attempted to develop WSI as a method of making a supercomputer, starting Trilogy Systems in 1980 and garnering investments from Groupe Bull, Sperry Rand, and Digital Equipment Corporation, who (along with others) provided as estimated $230 million in financing. The design called for a 2.5â³ square chip with 1200 pins on the bottom. After burning through about one third of the capital with nothing to show for it, Amdahl eventually declared the idea would only work with a 99.99% yield, which would not happen for 100 years. There were several subsequent efforts in the 1980's, but none successful.
Another well-known problem is the field of wafer-scale integration technology is the impact of thermal expansion on external connectivity. More specifically, when a WSI microelectronic complex is connected to a circuit board by thousands of, for example, connectors positioned between the microelectronic complex and the circuit board, these connectors can be damaged due to the different rates of thermal expansion experience by the surfaces of the microelectronic comples and circuit board.
Taking for example a finished silicon wafer, packaged in a material such as ceramic, the wafer typically expands at a rate of 3 ppm/C. In contrast, the material of the circuit board typically expands at a rate of 20-40 ppm/C. Thus, as the two materials heat up, the two surfaces will expand at different rates, potentially damaging many of the connectors distributed between the wafer and the circuit board. See Norman, et al., U.S. Pat. No. 7,279,787.
The present disclosure solves these longstanding problems with existing technology.
SUMMARY
In the applicant's disclosure regarding Faraday Cages and siped compartments, two entirely different technologies (siped cushioning compartments and Faraday Cages) from two entirely different and unrelated fields of technology (âmacroâ athletic footwear and microelectronics), each with their own completely different art, have been integrated into a surprising new combination wherein the integrated structural components have simultaneous dual functions that are completely separate and unrelated.
Moreover, the integrated use of a sipe media both as a lubricant between the siped compartments and as a cooling media for a microchip (or other electronic component) to deal with the critical microprocessor heat dissipation problem is an additional surprising combination of two entirely separate technical functions that are completely different into a single new structural and material component with dual functions, again from entirely different and unrelated fields of art.
The applicant's semiconductor wafer computer disclosure solves the two longstanding problems that have heretofore made all such wafer-scale integration efforts fail.
First, the applicant's disclosure solves the longstanding inherent flaw intolerance problem discussed above by using microchips on the wafer that are personal computer systems on the chip (SoC), so that each wafer microchip can operate independently, including communicating with other wafer microchips, such as wirelessly in free space and/or waveguides by radio or optical device. In the applicant's approach, the wafer microchips that inherently are flawed during manufacture or fail in operation require no elaborate special handling like that described above. Generally, if they fail fatally, the remaining wafer microchips inherently ignore them since they do not communicate with other microchips; also, partial failure can be detected remotely and the microchip can be turned off, if necessary.
Second, the applicant's disclosure solves the longstanding unequal thermal expansion problem discussed above by reducing, even almost eliminating the need for pins, since both on wafer and off wafer communication by the independently functioning microchips (personal computer SoC's) on the wafer can be accomplished by radio or optics connections that do not require pins or require far fewer structural connections. In addition, the applicant's use of stacked semiconductor wafers, which can have very similar or identical materials and expansion rates, can obviate the need for conventional motherboards or reduce their role.
Moreover, since the personal computer microchips on the semiconductor wafer can operate independently, such as in conventional clusters of several or many or all of the personal computers on the wafer (or including personal computers off the wafer as well), the operations occurring on the wafer can be asynchronous. The applicant's disclosure thereby also solves the longstanding problem of synchronizing such wafer scale operations by obviating the need for synchronizing them, as would be necessary without the applicant's disclosure.
These and other features of the disclosure will become apparent from the detailed description that follows.
BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 1-9 of this application are FIGS. 1-6, 52, 61, 67, 74, and 79 of both the applicant's U.S. application Ser. No. 11/802,033 filed May 18, 2007 and published on Apr. 10, 2008 as Pub. No. US 2008/0083140 A1 and PCT Application PCT/US2007/011976 filed 18 May 2007 and published on 31 Jan. 2008 as Int. Pub. No. WO 2008/013594 A2, as well as U.S. application Ser. No. 11/802,930 filed May 25, 2007 and published on Apr. 17, 2008 as Pub. No. US 2008/0086916 A1; all three applications are incorporated herein by reference. In addition, FIGS. 1-6 (except 6 D- 6 F) of this application are FIGS. 83-88 of both the applicant's U.S. application Ser. No. 11/282,665 filed Nov. 21, 2005 and published on Nov. 9, 2006 as Pub. No. US 2006/0248749 A1 and PCT Application PCT/US2005/042341 filed 21 Nov. 2005 and published on 1 Jun. 2006 as Int. Pub. No. WO 2006/058013 A2, both of which are incorporated herein by reference.
FIG. 1A-4A show a frontal or sagittal plane cross section view of an example of a device 510 such as a flexible insert with a siped compartment or chamber or bladder.
FIGS. 1B-6B shows a horizontal plane view of a device 510 example.
FIG. 1C is an exploded perspective view showing the relationship of an insert device 510 , which has a siped compartment or chamber or bladder, with a midsole, bottom sole, and upper of a shoe or other footwear.
FIGS. 1D-1F show an example of the 510 invention using typical commercial air bladder embodiments as compartment 501 modified with outer compartment 500 .
FIGS. 5A-6A show a frontal or sagittal plane cross section view of an example of a device 510 such as a flexible insert with two siped compartments or chambers or bladders or combination.
FIG. 7A shows a computer laptop with the 510 / 511 / 513 inventions and FIG. 7B shows a semiconductor microchip with the 510 / 511 / 513 inventions.
FIGS. 7C-7D show additional examples of the 510 / 511 / 513 inventions applied to electronic game controllers and cell phone.
FIG. 8 is a chart showing approximate comparison of hardness scales.
FIGS. 9A-9C show a large urban telephone book lying flat, solid wooden block, and an upright very thick book to illustrate basic concepts of sipe flexibility and stability.
FIGS. 10-22 of this application are FIGS. 10A-10I, 16A-16Z, 16AA, and 16AB, 17A-17D, 21B, 22A, 23A-23E, 25A-25D, 26A-26C, 27A-27H, 28, 29A, 30A-30C, and 31 of both the applicant's U.S. application Ser. No. 10/802,049 filed May 17, 2004 and published on Oct. 28, 2004 as Pub. No. US 2004/0215931 A1.
FIGS. 10A-10I are simplified diagrams of a section of a computer network, such as the Internet, showing an embodiment of a system architecture utilizing an internal firewall to separate that part of a networked PC (including a system reduced in size to a microchip) that is accessible to the network for shared processing from a part that is kept accessible only to the PC user; also showing the alternating role that each PC in the network may play as either a master or slave in a shared processing operation involving one or more slave PC's in the network; and showing a home or business network system which can be configured as an Intranet; in addition, showing PC and PC microchips controlled by a controller (including remote) with limited or no processing capability; and showing PC and PC microchips in which an internal firewall 50 can be reconfigured by a PC user.
FIGS. 11A-11K show a new hierarchical network architecture for personal computers and/or microprocessors based on subdivision of parallel processing or multi-tasking operations through a number of levels down to a processing level.
FIGS. 12A-12D show an internal firewall 50 with a dual function, including that of protecting Internet users (and/or other network users sharing use) of one or mo
This application is a continuation of U.S. patent application Ser. No. 13/931,080 filed Jun. 28, 2013; which is a continuation of Ser. No. 13/769,292, filed Feb. 16, 2013, now abandoned; which is a continuation of U.S. patent application Ser. No. 12/292,769, filed Nov. 25, 2008, now U.S. Pat. No. 8,125,796, which is a continuation-in-part of U.S. patent application Ser. No. 12/292,553, filed Nov. 20, 2008, now U.S. Pat. No. 8,164,170, which is a non-provisional of U.S. Provisional Application No. 60/996,530, filed on Nov. 21, 2007, and U.S. Provisional Application No. 60/996,553, filed on Nov. 26, 2007. U.S. patent application Ser. No. 12/292,769, filed Nov. 25, 2008, is also a non-provisional of U.S. Provisional Application No. 60/996,553, filed on Nov. 26, 2007. The contents of all of the above-mentioned applications are hereby incorporated herein by reference.
BACKGROUND
1. Field of the Disclosure
The disclosure relates to a Faraday Cage surrounding semiconductor microchips, photovoltaic cells, and/or other micro and/or nano devices combined with the applicant's prior internal sipe inventions, including at least one compartment surrounded by at least one internal sipe, such as a slit. More specifically, a Faraday Cage coincides with an outer compartment, which forms one surface of a sipe surrounding an inner compartment including a personal computer microchip and/or a photovoltaic cell and/or a fuel cell and/or a battery.
The disclosure also relates to a semiconductor wafer, such as silicon, containing a multitude of microchips, such as with one or more core microprocessors. Instead of separating the microchips into separate dies in the conventional process, the entire semiconductor wafer is used essentially intact as a computer. More specifically, interconnects can be added to the printed circuit architecture of the wafer to connect the wafer microchips to other wafer microchips and/or other components on the wafer or external to it. Still more specifically, each microchip can be a complete system on a chip (SoC). Even more specifically, the semiconductor wafer can be used with other conventional interface devices for power and data, including wireless such as radio and/or optic, and/or wired such as fiber optic and/or electric, including for each SoC microchip on the wafer. In another specific embodiment, two or more semiconductor wafers can be stacked in vertical layers; for example, with a first wafer including microprocessors or cores; a second wafer including random access memory or RAM; and a third wafer including other components; each SoC microchip, in this example, can have one or more components on each of the three wafers.
The disclosure also relates to the semiconductor wafer including one or more of the applicant's prior internal sipe inventions, with an outer compartment having an internal sipe.
The disclosure also relates to the semiconductor wafer being surrounded by one or more Faraday Cages integrated into the internal sipe invention.
2. Brief Description of the Prior Art
Faraday Cage surrounding semiconductor microchips, photovoltaic cells, and/or other micro and/or nano devices, are described by the applicant in his U.S. application Ser. No. 10/802,049 filed Mar. 17, 2004, and published as Pub. No. US 2004/0215931 A1 on Oct. 28, 2004.
The applicant's prior internal footwear sipe inventions, including at least one compartment surrounded by at least one internal sipe, such as a slit, are described by the applicant in his U.S. patent application Ser. No. 11/802,930, filed May 25, 2007 and published as Pub. No. US 2008/0086916 A1 on Apr. 17, 2008, as well as in several earlier U.S. applications filed by the applicant.
Existing semiconductor wafers, currently up to 300 mm in diameter, are always cut into a large number of separate dies, with one microchip formed into a package from each flaw-free die cut from the semiconductor wafer; some dies are inherently defective and are discarded. A typical semiconductor wafer is shown in the applicant's U.S. application Ser. No. 10/684,657 filed Oct. 15, 2003.
As described in Wikipedia, âwafer scale integrationâ (WSI) is a yet-unused system of building very-large integrated circuit networks that use an entire silicon wafer to produce a single âsuper-chip.â Through a combination of large size and reduced packaging, WSI could lead to dramatically reduced costs for some systems, notably massively parallel supercomputers.
Many companies including TI and ITT attempted to develop âwafer scale integrationâ (WSI) production systems in the 1970's and '80's, but all failed and no products were released. Further attempts at WSI appear to be largely abandoned for decades.
One critical problem that has not been overcome is that of inherent flaws in semiconductor wafers. It has been an ongoing goal to develop methods to handle faulty areas of the wafers through logic, as opposed to sawing them out of the wafer. Generally, this approach uses a grid pattern of sub-circuits and ârewiresâ around the damaged areas using appropriate logic.
The overwhelming difficulty of this approach is illustrated by the history of famous computer pioneer Gene Amdahl, who attempted to develop WSI as a method of making a supercomputer, starting Trilogy Systems in 1980 and garnering investments from Groupe Bull, Sperry Rand, and Digital Equipment Corporation, who (along with others) provided as estimated $230 million in financing. The design called for a 2.5â³ square chip with 1200 pins on the bottom. After burning through about one third of the capital with nothing to show for it, Amdahl eventually declared the idea would only work with a 99.99% yield, which would not happen for 100 years. There were several subsequent efforts in the 1980's, but none successful.
Another well-known problem is the field of wafer-scale integration technology is the impact of thermal expansion on external connectivity. More specifically, when a WSI microelectronic complex is connected to a circuit board by thousands of, for example, connectors positioned between the microelectronic complex and the circuit board, these connectors can be damaged due to the different rates of thermal expansion experience by the surfaces of the microelectronic comples and circuit board.
Taking for example a finished silicon wafer, packaged in a material such as ceramic, the wafer typically expands at a rate of 3 ppm/C. In contrast, the material of the circuit board typically expands at a rate of 20-40 ppm/C. Thus, as the two materials heat up, the two surfaces will expand at different rates, potentially damaging many of the connectors distributed between the wafer and the circuit board. See Norman, et al., U.S. Pat. No. 7,279,787.
The present disclosure solves these longstanding problems with existing technology.
SUMMARY
In the applicant's disclosure regarding Faraday Cages and siped compartments, two entirely different technologies (siped cushioning compartments and Faraday Cages) from two entirely different and unrelated fields of technology (âmacroâ athletic footwear and microelectronics), each with their own completely different art, have been integrated into a surprising new combination wherein the integrated structural components have simultaneous dual functions that are completely separate and unrelated.
Moreover, the integrated use of a sipe media both as a lubricant between the siped compartments and as a cooling media for a microchip (or other electronic component) to deal with the critical microprocessor heat dissipation problem is an additional surprising combination of two entirely separate technical functions that are completely different into a single new structural and material component with dual functions, again from entirely different and unrelated fields of art.
The applicant's semiconductor wafer computer disclosure solves the two longstanding problems that have heretofore made all such wafer-scale integration efforts fail.
First, the applicant's disclosure solves the longstanding inherent flaw intolerance problem discussed above by using microchips on the wafer that are personal computer systems on the chip (SoC), so that each wafer microchip can operate independently, including communicating with other wafer microchips, such as wirelessly in free space and/or waveguides by radio or optical device. In the applicant's approach, the wafer microchips that inherently are flawed during manufacture or fail in operation require no elaborate special handling like that described above. Generally, if they fail fatally, the remaining wafer microchips inherently ignore them since they do not communicate with other microchips; also, partial failure can be detected remotely and the microchip can be turned off, if necessary.
Second, the applicant's disclosure solves the longstanding unequal thermal expansion problem discussed above by reducing, even almost eliminating the need for pins, since both on wafer and off wafer communication by the independently functioning microchips (personal computer SoC's) on the wafer can be accomplished by radio or optics connections that do not require pins or require far fewer structural connections. In addition, the applicant's use of stacked semiconductor wafers, which can have very similar or identical materials and expansion rates, can obviate the need for conventional motherboards or reduce their role.
Moreover, since the personal computer microchips on the semiconductor wafer can operate independently, such as in conventional clusters of several or many or all of the personal computers on the wafer (or including personal computers off the wafer as well), the operations occurring on the wafer can be asynchronous. The applicant's disclosure thereby also solves the longstanding problem of synchronizing such wafer scale operations by obviating the need for synchronizing them, as would be necessary without the applicant's disclosure.
These and other features of the disclosure will become apparent from the detailed description that follows.
BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 1-9 of this application are FIGS. 1-6, 52, 61, 67, 74, and 79 of both the applicant's U.S. application Ser. No. 11/802,033 filed May 18, 2007 and published on Apr. 10, 2008 as Pub. No. US 2008/0083140 A1 and PCT Application PCT/US2007/011976 filed 18 May 2007 and published on 31 Jan. 2008 as Int. Pub. No. WO 2008/013594 A2, as well as U.S. application Ser. No. 11/802,930 filed May 25, 2007 and published on Apr. 17, 2008 as Pub. No. US 2008/0086916 A1; all three applications are incorporated herein by reference. In addition, FIGS. 1-6 (except 6 D- 6 F) of this application are FIGS. 83-88 of both the applicant's U.S. application Ser. No. 11/282,665 filed Nov. 21, 2005 and published on Nov. 9, 2006 as Pub. No. US 2006/0248749 A1 and PCT Application PCT/US2005/042341 filed 21 Nov. 2005 and published on 1 Jun. 2006 as Int. Pub. No. WO 2006/058013 A2, both of which are incorporated herein by reference.
FIG. 1A-4A show a frontal or sagittal plane cross section view of an example of a device 510 such as a flexible insert with a siped compartment or chamber or bladder.
FIGS. 1B-6B shows a horizontal plane view of a device 510 example.
FIG. 1C is an exploded perspective view showing the relationship of an insert device 510 , which has a siped compartment or chamber or bladder, with a midsole, bottom sole, and upper of a shoe or other footwear.
FIGS. 1D-1F show an example of the 510 invention using typical commercial air bladder embodiments as compartment 501 modified with outer compartment 500 .
FIGS. 5A-6A show a frontal or sagittal plane cross section view of an example of a device 510 such as a flexible insert with two siped compartments or chambers or bladders or combination.
FIG. 7A shows a computer laptop with the 510 / 511 / 513 inventions and FIG. 7B shows a semiconductor microchip with the 510 / 511 / 513 inventions.
FIGS. 7C-7D show additional examples of the 510 / 511 / 513 inventions applied to electronic game controllers and cell phone.
FIG. 8 is a chart showing approximate comparison of hardness scales.
FIGS. 9A-9C show a large urban telephone book lying flat, solid wooden block, and an upright very thick book to illustrate basic concepts of sipe flexibility and stability.
FIGS. 10-22 of this application are FIGS. 10A-10I, 16A-16Z, 16AA, and 16AB, 17A-17D, 21B, 22A, 23A-23E, 25A-25D, 26A-26C, 27A-27H, 28, 29A, 30A-30C, and 31 of both the applicant's U.S. application Ser. No. 10/802,049 filed May 17, 2004 and published on Oct. 28, 2004 as Pub. No. US 2004/0215931 A1.
FIGS. 10A-10I are simplified diagrams of a section of a computer network, such as the Internet, showing an embodiment of a system architecture utilizing an internal firewall to separate that part of a networked PC (including a system reduced in size to a microchip) that is accessible to the network for shared processing from a part that is kept accessible only to the PC user; also showing the alternating role that each PC in the network may play as either a master or slave in a shared processing operation involving one or more slave PC's in the network; and showing a home or business network system which can be configured as an Intranet; in addition, showing PC and PC microchips controlled by a controller (including remote) with limited or no processing capability; and showing PC and PC microchips in which an internal firewall 50 can be reconfigured by a PC user.
FIGS. 11A-11K show a new hierarchical network architecture for personal computers and/or microprocessors based on subdivision of parallel processing or multi-tasking operations through a number of levels down to a processing level.
FIGS. 12A-12D show an internal firewall 50 with a dual function, including that of protecting Internet users (and/or other network users sharing use) of one or more slave personal computers PC 1 or microprocessors 40 from unauthorized surveillance or intervention by an owner/operator of those slave processors.
FIG. 13 shows that all microprocessors of a personal computer or personal computer on a microchip can have a separate input/output communication link to a digital signal processor (DSP) or other transmission/reception connection component.
FIGS. 14A-C show a PC microprocessor on a microchip similar to that of FIG. 13 , except that FIGS. 14A- C
show microprocessors
93 and 94 each connecting to an optical wired connection 99 â² such as thin mirrored hollow wire or optical omniguide or optical fiber.
FIGS. 15A-E show multiple firewalls 50 within a personal computer 1 or PC microchip 90 .
FIGS. 16A-D show the use for security of power interruption or data overwrite of volatile memory like DRAM and non-volatile memory like Flash or MRAM (or ovonics), respectively, of the network portion of a personal computer PC 1 or system on a microchip PC 90 .
FIGS. 17A-C show exemplary microchip and photovoltaic cell embodiments.
FIGS. 18A-H show exemplary microchip and Faraday Cage embodiments.
FIG. 19 shows a silicon wafer 500 used to make microchips.
FIG. 20A shows a top view of a microchip 501 surrounded by adjoining portions of adjoining microchips 501 in a section of the silicon wafer 500 . FIG. 20B shows a top view of the microchip 501 embodiment of FIG. 20A after the die has been separated from the silicon wafer 500 and positioned in a microchip package 503 .
FIGS. 21A-C show alternative embodiments that unite separate fabrication processes on the same microchip 501 .
FIG. 22 shows a combination of the embodiments shown in FIGS. 20 and 21 .
FIGS. 23A-23H are modifications of FIGS. 18A-27H of this application, which are FIGS. 27A-27H of U.S. application Ser. No. 10/802,049 filed Mar. 17, 2004 and published on Oct. 28, 2004, as Pub. No. US 2004/0215931 A1 and U.S. application Ser. No. 10/684,657 filed Oct. 15, 2003 and published on Aug. 18, 2005, as Pub. No. US 2005/0180095 A1, both of which applications are hereby incorporated by reference herein for completeness of disclosure.
FIGS. 23A-23H are more specific example embodiments of the FIG. 7B example; they show examples of the applicant's inventions involving one or more Faraday Cages surrounding various combinations of semiconductor microchips, photovoltaic cells, and/or other micro and/or nano devices with the applicant's internal sipe inventions 510 / 511 / 513 .
FIGS. 24A and 25A-25B are modifications of FIGS. 28 and 29A-29B of U.S. application Ser. No. 10/684,657 filed Oct. 15, 2003 and published on Aug. 18, 2005, as Pub. No. US 2005/0180095 A1, which was above incorporated by reference herein for completeness of disclosure.
FIG. 24A is a top view of a semiconductor wafer 1500 , the entire semiconductor wafer 1500 being used essentially intact as a computer, which can also include a Faraday Cage and a siped compartment. FIG. 24B is a side cross section of three stacked wafers 1500 . FIG. 24C is another top view of a wafer 1500 , but subdivided into smaller components, such as half sections and quarter sections.
FIGS. 25A-25B are modifications of FIGS. 29A-29B of the '657 application incorporated by reference herein above. FIG. 25B shows a microchip 1501 as a separated die in a package 1503 including the applicant's internal sipe inventions 510 / 511 / 513 and the Faraday Cage 300 .
FIGS. 26A-26B is FIGS. 7A-7B with the addition of Faraday Cages, as well as stacked dies in FIG. 7B .
FIGS. 27A-27B are like FIGS. 28A-28B of the '033 and '930 Applications incorporated above shows in cross-section an example of a tire 535 , such as for a wheel 533 of a transportation vehicle, with a device 510 .
It is understood that the reference numbers identified in this application and in U.S. Patent Applications '665, '033, and '930 incorporated by reference herein, are used consistently throughout the application such that like reference numbers are used to describe the same or like elements.
DETAILED DESCRIPTION
FIGS. 1-9 of this application are FIGS. 1-6, 52, 61, 67, 74, and 79 of both the applicant's U.S. application Ser. No. 11/802,033 filed May 18, 2007 and published on Apr. 10, 2008 as Pub. No. US 2008/0083140 A1 and PCT Application PCT/US2007/011976 filed 18 May 2007 and published on 31 Jan. 2008 as Int. Pub. No. WO 2008/013594 A2, as well as U.S. application Ser. No. 11/802,930 filed May 25, 2007 and published on Apr. 17, 2008 as Pub. No. US 2008/0086916 A1; all three applications are incorporated herein by reference. In addition, FIGS. 1-6 (except 6 D- 6 F) of this application are FIGS. 83-88 of both the applicant's U.S. application Ser. No. 11/282,665 filed Nov. 21, 2005 and published on Nov. 9, 2006 as Pub. No. US 2006/0248749 A1 and PCT Application PCT/US2005/042341 filed 21 Nov. 2005 and published on 1 Jun. 2006 as Int. Pub. No. WO 2006/058013 A2, both of which are incorporated herein by reference.
FIGS. 1-9 show the applicant's prior inventions incorporating forms of insertable devices with one or more internal (or mostly internal) sipes, including slits (or channels or grooves and other shape, including geometrically regular or non-regular shapes, such as anthropomorphic shapes), into a large variety of products, including footwear and orthotics, athletic, occupational and medical equipment and apparel, padding for equipment and furniture, balls, tires and any other structural or support elements in a mechanical, architectural or any other device.
New reference numerals used in the FIGS. 1-79 are further defined as follows:
Ref. No 500 : An outer compartment, such as an outer compartment 161 or chamber 188 or bladder, at least partially or mostly or entirely enclosing a space within the outer compartment/chamber/ bladder 500 , which can be located anywhere in a footwear sole or upper or both or other article described in this application. Construction and materials can be, as one embodiment example, simpler in shape but otherwise similar to those used in any commercial samples of Nike Airâ¢. Ref. No 501 : An inner compartment, such as an inner compartment 161 or chamber 188 or bladder, is located inside the enclosed space of the outer compartment/chamber/ bladder 500 . Construction and materials of the inner compartment/chamber/ bladder 501 can be, as one embodiment example, like those used in any commercial samples of gas bladders in Nike Airâ¢. Ref. No. 502 : Structural element that is optional anywhere within either outer compartment/chamber/ bladder 500 or inner compartment/chamber/ bladder 501 , of which a 501 embodiment is shown; any flexible, resilient material can be used, including structures molded into the shape of (and using the material of) the compartment/chamber/ bladder
500 or 501 , as is very common in the art, such as many commercial samples of gas bladders used in Nike Airâ¢, as well as foamed plastic or plastic composite or other materials, like Nike Shox⢠or Impax⢠or Reebok DMX⢠or New Balance N-ergyâ¢. In addition, other materials can be used directly within a 501 / 500 compartment or can connected to or through a 501 / 500 compartment, as in the cushioning components of the shoe sole heel of commercial samples of Adidas 1â¢, including electromechanical, electronic, and other components. Some devices may benefit from the use of rigid or semi-rigid materials for part or all of a media within a compartment. Ref. No. 503 : Attachment of two compartment/chambers/ bladders 500 / 501 , including particularly attachment of outer 500 to inner 501 ; any practical number of attachments of any form using any materials can be used, including glue. Ref. No. 504 : Media contained within all or part of compartment/chamber/ bladder
500 or 501 , particularly 501 , can be any useful material, such as gas (including, as an example, gas used in Nike Air⢠or ambient air, liquid or fluid, gel, or foam (such as a plastic like PU or EVA or equivalent or rubber (natural or synthetic) or combination of two or more; encapsulation of foam is optional); material particles or coatings, such as dry coatings like Teflon⢠can also be used. An optional element in an outer compartment/chamber 500 (or an inner compartment/ chamber 501 that itself contains an inner compartment/chamber, as in FIG. 87 ). Ref. No. 505 : Internal sipe or slit or channel or groove for flexibility, such as between inner and outer compartment/ chamber 500 / 501 (or bladder) surfaces, as one embodiment example; such surfaces can be substantially parallel and directly contact in one useful embodiment example, but are not attached so that at least parts of the two surfaces can move relative to each other, such as to facilitate a sliding motion between surfaces; the surfaces can be in other useful forms that allow portions of the surfaces to be proximate to each other but not contacting in an unloaded condition or in a partially loaded condition or in a maximally loaded condition. Ref. No. 506 : Media of internal sipe 505 ; media 506 can be any useful material like those used in media 504 ; media 506 can be located in part or all of 505 to decrease (or increase) sliding resistance between 500 / 501 or 505 surfaces, for example, to lubricate the surfaces with any suitable material; silicone or Teflon⢠can be used, for example; an optional element. Ref. No. 507 : Metal particles. Ref. No. 508 : Shock absorbing fluid containing 507 ; a magnetorheological fluid. Ref. No. 509 : Electromagnetic field-creating circuit. Ref. No. 510 : A flexible insert or component including siped compartments 161 or chambers 188 or bladders used for example as outer and inner compartments/chambers/ bladders 500 / 501 for footwear soles or orthotics or uppers or other uses; a useful embodiment being two or more compartment or chambers (or bladders) 161 / 188 (or mix) that are separated at least in part by an internal sipe 505 , including the example of at least one 501 (either 161 / 188 or bladder) inside at least one 500 (either 161 / 188 or bladder) and being separated by an internal sipe 505 . Ref. No. 580 : Computer or computer component. Ref. No. 581 : Micro-technology and nanotechnology devices, including a semiconductor microchip device (a part of a die or an entire die or multiple dies assembled together) microelectromechanical systems (MEMS), field-programmable gate arrays (FPGA's) and faraday cages, photovoltaic cells, fuel cells, batteries, and including devices assembled at the molecular or atomic scale.
FIGS. 1-7 show, as numeral 510 , examples of a device or flexible insert including siped compartments 161 or chambers 188 or bladders (another term used in the art) for use in any footwear soles, including conventional soles 22 or the applicant's prior inventions, including footwear/shoe soles 28 and midsole inserts 145 as described in applicant's published '087 Application and Ser. No. 11/282,665 U.S. Application published Nov. 9, 2006, as Pub. No. US 2006/0248749 A1 incorporated by reference, or for orthotics 145 as described in the applicant's published '034 U.S. Application, '869 Patent, and WO 02/09547 WIPO publication, as well as to be published by WIPO PCT Application Number PCT/US2005/042341, all incorporated by reference herein, including for uppers for footwear or orthotics (or including uppers), or for other flexibility uses in athletic equipment like helmets and apparel including protective padding and guards, as well as medical protective equipment and apparel, and other uses, such as protective flooring, improved furniture cushioning, balls and tires for wheels, and other uses.
The device or flexible insert with siped compartments or chambers 510 include embodiments like two or more of either compartments 161 or chambers 188 or bladders (or a any mix including two or more of a compartment, a chamber, and a bladder) that are separated at least in part or in several parts or mostly or fully by an internal sipe 505 . The flexible insert 510 can be inserted during assembly of an article by a maker or manufacturer or is insertable by a user or wearer (into an article like a shoe, for example, as part of a removable midsole insert 145 described above), or integrated into the construction of a device as one or more components.
Siped compartments or chambers 510 include example embodiments such as FIGS. 1-7 , which generally show at least one inner compartment 161 or chamber 188 inside at least one other outer compartment 161 or chamber 161 ; and the two compartments/chambers 161 / 188 being separated by an internal sipe 505 .
One practical example embodiment of the invention is any prior commercial embodiment of Nike Air⢠gas bladder or compartment (like typical examples in FIGS. 12-16 of U.S. Pat. No. 6,846,534, which is hereby incorporated by reference) that is installed unattached, as is, located within the space enclosed partially or fully by a new, slightly larger outer compartment of one additional layer of the same or similar material, with the same or a simpler or the simplest geometric shape; that is, not necessarily following indentations or reverse curves, but rather incorporating straighter or the straightest lines, as seen in cross-section: for example, following the outermost side curvature seen in FIGS. 12-16 , but with upper and lower surfaces that are substantially flat and parallel (or curved and parallel), to facilitate ease of movement between the two surfaces of the sipe 505 formed, increasing the resulting flexibility.
The new additional, outer compartment thus thereby has created by its presence an internal sipe 505 between the two unconnected compartments. The new internal sipe 505 provides much greater flexibility to any footwear sole 22 or 28 , since it allows an inner, otherwise relatively rigid Nike Air⢠compartment structure to become an inner compartment 501 (instead of typically being fixed into the other materials such as EVA of the footwear sole) to move freely inside the new outer compartment 500 , which becomes a new compartment that is fixed to the footwear sole, rather that the conventional Nike Air⢠bladder. The flexibility improvement allows the shoe sole to deform under a body weight load like a wearer's bare foot sole, so that stability is improved also, especially lateral stability.
The result is that the conventional, inner Nike Air⢠compartmentânow contained by a new outer compartmentâcan move easily within the overall footwear sole, allowing the sole to bend or flex more easily in parallel with the wearer's bare foot sole to deform to flatten under a body weight load, including during locomotion or standing, so that footwear sole stability is improved also, especially lateral stability. The extent to which the inner Nike Air⢠compartment is âfree-floatingâ within the new outer compartment can be controlled or tuned, for example, by one or more attachments (permanent or adjustable) to the outer compartment or by the media in the internal sipe.
The internal sipe 505 includes at least two surfaces that can move relative to each other to provide a flexibility increase for a footwear sole so that the shape of the footwear sole can deform under a body weight load to better parallel to the shape of the barefoot sole of a wearer under a same body weight load. The relative motion between the two internal sipe 505 surfaces increases the capability of the footwear sole to bend during locomotion under a wearer's body weight load to better parallel the shape of said wearer's bare foot sole.
Also, the sliding motion between internal support surfaces within the shoe sole 28 allowed by internal sipe 505 in response to torsional or shear forces between a wearer's foot and the ground assists in controlling and absorbing the impact of those forces, whether sudden and excessive or chronically repetitive, thereby helping to protect the wearer's joints from acute or chronic injury, especially to the ankles, knees, hips, lower back, and spine.
A benefit of the siped compartments/ chambers 510 is that, as a single unitary component, it can be used in any conventional manner in constructing the footwear sole 28 , generally like that used with a conventional single layer compartment such as used in Nike Airâ¢; i.e. the outer surface of 510 can, as a useful embodiment, adhere to the adjacent materials like plastic such as PU (polyurethane) or EVA (ethyl vinyl acetate) or other plastic or rubber of the footwear sole that contact the 510 component, just as would be the case with the outer surface of existing single compartment 161 or chamber 188 of commercial examples of Nike Airâ¢. However, the internal sipe 505 formed by the use of an inner compartment/ chamber 501 in the siped compartment/ chamber 510 provides flexibility in a footwear sole 28 that is absent in the relatively rigid footwear sole 28 formed with a conventional, single layer compartment 161 or chamber 188 of the many Nike Air⢠commercial examples.
The sipe surfaces can in one useful example embodiment be formed by the inner surface (or part or parts of it) of the outer compartment 500 and the outer surface (or part or parts of it) of the inner compartment 501 . Such sipe surfaces can be substantially parallel and directly contact each other in one useful embodiment example, but the two surfaces are generally not attached to each other, so that the sipe surfaces can move relative to each other to facilitate a sliding motion between the two surfaces.
The sipe surfaces can be in other useful forms that allow portions of the surfaces to be proximate to each other in an unloaded condition, rather than contacting; such surfaces can make partial or full direct contact under a wearer's body weight load (which can vary from a fraction of a âgâ to multiple âgâ forces during locomotion) or remain somewhat separated; the amount of sipe surface area making direct contact can also vary with a wearer's body weight load. The sipes surfaces also may not be parallel or only partially parallel, such as the areas of direct surface contact or proximal surface contact.
To preclude the surfaces of the internal sipe 505 from directly contacting each other (whether loaded or unloaded), the sipe surfaces can include an internal sipe media 506 located between the surfaces to reduce friction by lubrication and increase relative motion and therefore flexibility. Useful example embodiments of the internal sipe media 506 include any useful material known in the art (or equivalent), such as a liquid like silicone as one example, a dry material like Teflon⢠as another example, or a gas like that used in Nike Air⢠as a further example. The media 506 can be located in all of the sipe 505 or only part or parts, as shown in FIGS. 1-6 .
The media 506 can be used to decrease (or increase) sliding resistance between the inner surfaces of the sipe; for example, to lubricate with any suitable material known in the art. The internal sipe media 506 is an optional feature.
The attachments 503 can be simply passive (i.e. static) or actively controlled by electronic, mechanical, electromagnetic, or other useful means. The attachments 503 can, for example, be designed to break away as a failsafe feature to compensate for a predetermined extreme torsional load, for example, to reduce extreme stress on critical joints (in lieu of a wearer's cartilage, tendons, muscle, bone, or other body parts being damaged); the attachments 503 can then be reset or replaced (or, alternatively, return automatically upon relief of extreme stress to a normal position).
Example embodiments of the compartments and chambers 500 / 501 can include a media 504 such as a gas (like that used in Nike Air⢠or ambient atmospheric air), a liquid or fluid, a gel, a foam (made of a plastic like PU or EVA, both of which are common in the footwear art, or equivalent, or of a rubber (natural or synthetic) or blown rubber or a rubber compound or equivalent or of another useful material or of a combination of two or more of the preceding foam plastic/rubber/etc.) or a useful combination of one or more gas, liquid, gel, foam, or other useful material.
FIGS. 2A, 3A, and 4A show examples of embodiments of siped compartment/chamber/ bladders 510 wherein either the inner compartment/chamber/ bladder 501 or the outer compartment 500 can have one or more openings, for pressure equalization, assembly facilitation, or other purposes.
FIG. 5A shows an example embodiment with an inner compartment/chamber/ bladder 501 1 having a smaller inner compartment/chamber/ bladder 501 2 ; additional smaller inner compartments 501 are possible in a similar progression, either enclosed within the previous larger inner compartment 501 or within the same 501 or 500 .
FIG. 6A shows an example embodiment with two inner compartment/chamber/ bladders
501 1 and 501 2 which are layered within outer compartment/chamber/ bladder 500 ; additional compartment/ chamber 501 layers can be useful also.
FIG. 1B shows an example embodiment of the <figure-callout id="510" label="device" filenames="US09568946-20170214-D00001.png,US09568946-20170214-D0000
CLAIMS
Claims ( 17 )
What is claimed is:
1. A microchip comprising:
at least one outer chamber, compartment, or bladder;
at least one inner chamber, compartment, or bladder inside said outer chamber, compartment, or bladder;
at least one internal sipe separating at least a part of said outer chamber, compartment, or bladder and at least a part of said inner chamber, compartment, or bladder;
at least one Faraday cage; and
said microchip being configured to connect to at least one network of computers, said microchip comprising at least a first internal hardware firewall configured to deny access to at least a first protected portion of said microchip from said network; and
wherein said at least one internal sipe is formed by at least a portion of an inner surface of said outer chamber, compartment, or bladder and at least a portion of an outer surface of said inner chamber, compartment, or bladder; and
the inner and outer surface portions forming said at least one internal sipe oppose each other and can move relative to each other in a sliding motion; and
wherein at least a portion of an outer surface of said outer chamber, compartment, or bladder is proximate to an outer surface of said microchip.
2. The microchip according to claim 1 , wherein said at least one outer chamber, compartment, or bladder includes at least one said Faraday Cage.
3. The microchip according to claim 1 , wherein said microchip comprises at least one general purpose microprocessor including at least two general purpose core or general purpose processing units, and wherein
at least a first said core or processing unit is located within said first protected portion of said microchip that is protected by at least said first internal hardware firewall;
at least a second said core or processing unit is located within a second portion of said microchip that is not protected by at least said first internal hardware firewall; and
at least said second core or processing unit is separated from said first core or processing unit by at least said first internal hardware firewall and is located between at least said first internal hardware firewall and said at least one network of computers.
4. The microchip according to claim 3 , wherein said microchip further comprises a master controller of the microprocessor located within said first protected portion of said microchip that is protected by at least said first internal hardware firewall, and said master controller is configured to control said second said core or processing unit.
5. The microchip according to claim 1 , wherein said microchip further comprises a wire cable configured for electronic devices, said wire cable comprising:
at least one wire;
at least one inner layer surrounding a portion of said at least one wire;
at least one outer layer surrounding a portion of said at least one inner layer; and
at least one internal sipe of said wire cable separating at least a part of one said outer layer and at least a part of one said inner layer;
wherein said at least one internal sipe of said wire cable is formed by at least a portion of an inner surface of said outer layer and at least a portion of an outer surface of said inner layer; and
the inner layer and outer layer surface portions of said wire cable forming said at least one internal sipe of said wire cable oppose each other and can move relative to each other in a sliding motion.
6. A microchip comprising:
at least one outer chamber, compartment, or bladder;
at least one inner chamber, compartment, or bladder inside said outer chamber, compartment, or bladder;
at least one internal sipe separating at least a part of said outer chamber, compartment, or bladder and at least a part of said inner chamber, compartment, or bladder;
said microchip being configured to connect to at least one network of computers, said microchip comprising at least four internal hardware firewalls, said at least four internal hardware firewalls configured to deny access to at least four protected portions of said microchip from said network of computers;
at least one Faraday cage; and
wherein said at least one internal sipe is formed by at least a portion of an inner surface of said outer chamber, compartment, or bladder and at least a portion of an outer surface of said inner chamber, compartment, or bladder; and
the inner and outer surface portions forming said at least one internal sipe oppose each other and can move relative to each other in a sliding motion; and
wherein at least a portion of an outer surface of said outer chamber, compartment, or bladder is proximate to an outer surface of said microchip.
7. The microchip according to claim 6 , wherein said at least one outer chamber, compartment, or bladder includes at least one said Faraday Cage.
8. The microchip according to claim 6 , wherein said microchip comprises at least one general purpose microprocessor including at least two general purpose core or general purpose processing units, and wherein
at least a first said core or processing unit is located within said first protected portion of said microchip that is protected by at least said first internal hardware firewall;
at least a second said core or processing unit is located within a second portion of said microchip that is not protected by at least said first internal hardware firewall; and
at least said second core or processing unit is separated from said first core or processing unit by at least said first internal hardware firewall and is located between at least said first internal hardware firewall and said at least one network of computers.
9. The microchip according to claim 8 , wherein said microchip further comprises a master controller of the microprocessor located within said first protected portion of said microchip that is protected by at least said first internal hardware firewall, and said master controller is configured to control said second said core or processing unit.
10. The microchip according to claim 6 , wherein said microchip further comprises a wire cable configured for electronic devices, said wire cable comprising:
at least one wire;
at least one inner layer surrounding a portion of said at least one wire;
at least one outer layer surrounding a portion of said at least one inner layer; and
at least one internal sipe of said wire cable separating at least a part of one said outer layer and at least a part of one said inner layer;
wherein said at least one internal sipe of said wire cable is formed by at least a portion of an inner surface of said outer layer and at least a portion of an outer surface of said inner layer; and
the inner layer and outer layer surface portions of said wire cable forming said at least one internal sipe of said wire cable oppose each other and can move relative to each other in a sliding motion.
11. The microchip according to claim 6 , wherein said microchip comprises at least one general purpose microprocessor with at least four general purpose cores or general purpose processing units, each protected by at least one of said at least four internal hardware firewalls.
12. A microchip comprising:
at least one outer chamber, compartment, or bladder;
at least one inner chamber, compartment, or bladder inside said outer chamber, compartment, or bladder;
at least one internal sipe separating at least a part of said outer chamber, compartment, or bladder and at least a part of said inner chamber, compartment, or bladder;
at least one Faraday cage; and
said microchip being configured to connect to at least one network of computers, said microchip comprising at least a first internal hardware firewalls configured to deny access to at least a first protected portion of said microchip from said network; and
the microchip further including at least one general purpose microprocessor with at least a general purpose core or processing unit including a master controller of the microprocessor and at least one general purpose core or general purpose processing unit; and
wherein said at least one internal sipe is formed by at least a portion of an inner surface of said outer chamber, compartment, or bladder and at least a portion of an outer surface of said inner chamber, compartment, or bladder; and
the inner and outer surface portions forming said at least one internal sipe oppose each other and can move relative to each other in a sliding motion; and
wherein at least a portion of an outer surface of said outer chamber, compartment, or bladder is proximate to an outer surface of said microchip.
13. The microchip according to claim 12 , wherein said at least one outer chamber, compartment, or bladder includes at least one said Faraday Cage.
14. The microchip according to claim 12 , wherein said at least one general purpose microprocessor includes at least two general purpose cores or general purpose processing units, and wherein
at least a first said core or processing unit is located within said first protected portion of said microchip that is protected by at least said first internal hardware firewall;
at least a second said core or processing unit is located within a second portion of said microchip that is not protected by at least said first internal hardware firewall; and
at least said second core or processing unit is separated from said first core or processing unit by at least said first internal hardware firewall and is located between at least said first internal hardware firewall and said at least one network of computers.
15. The microchip according to claim 14 , wherein said master controller of the microprocessor is located within said first protected portion of said microchip that is protected by at least said first internal hardware firewall, and said master controller is configured to control said second said core or processing unit.
16. The microchip according to claim 12 , wherein the master controller of the microprocessor is also protected by a second said internal hardware firewall.
17. The microchip according to claim 12 , wherein said microchip further comprises a wire cable configured for electronic devices, said wire cable comprising:
at least one wire;
at least one inner layer surrounding a portion of said at least one wire;
at least one outer layer surrounding a portion of said at least one inner layer; and
at least one internal sipe of said wire cable separating at least a part of one said outer layer and at least a part of one said inner layer;
wherein said at least one internal sipe of said wire cable is formed by at least a portion of an inner surface of said outer layer and at least a portion of an outer surface of said inner layer; and
the inner layer and outer layer surface portions of said wire cable forming said at least one internal sipe of said wire cable oppose each other and can move relative to each other in a sliding motion.
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