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Computer or microchip controlled by a firewall-protected master controlling … — Frampton E. Ellis (US9531671B2)

Frampton E. Ellis · Google Patents

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patent, google patents, intellectual property, US9531671B2, Frampton E. Ellis, en, 2016

ABSTRACT

Abstract

A computer or microchip including a master controlling microprocessor and firmware, network communication components, one or more microprocessors and RAM, and an internal hardware firewall located between a protected portion that is protected by the internal hardware firewall and a network portion. The internal hardware firewall denies access to at least the protected portion of the computer or microchip from the network. The firewall permits unrestricted access by the network to the network portion so that processing operations conducted with the network are executed by microprocessors and RAM in the network portion. The master controlling microprocessor and at least a part or all of the firmware are located in the protected portion of the computer or microchip. The master controlling microprocessor has preemptive control of the microprocessors and RAM in the network portion including erasure of the random access memory (RAM) prior to the use of the network portion.

Description

This application is a continuation of U.S. patent application Ser. No. 13/599,484, filed Aug. 30, 2012, which is a continuation of U.S. patent application Ser. No. 12/822,928, filed Jun. 24, 2010, now U.S. Pat. No. 8,291,485, which is a continuation of U.S. patent application Ser. No. 10/802,049, filed Mar. 17, 2004 (now U.S. Pat. No. 7,805,756), which is a continuation of International Application No. PCT/US02/29227, filed Sep. 16, 2002, which in turn claims the benefit of U.S. Provisional Application Nos. 60/322,474, filed Sep. 17, 2001, and 60/323,701, filed Sep. 21, 2001. U.S. patent application Ser. No. 10/802,049, filed Mar. 17, 2004, is also a continuation-in-part of U.S. patent application Ser. No. 09/935,779, filed Aug. 24, 2001 (now U.S. Pat. No. 7,506,020), which receives the benefit of priority from provisional applications 60/308,826, filed Aug. 1, 2001, and 60/227,660, filed Aug. 25, 2000. U.S. patent application Ser. No. 09/935,779 is a continuation-in-part of U.S. patent application Ser. No. 09/571,558, filed May 16, 2000 (now U.S. Pat. No. 7,035,906), which receives the benefit of priority from provisional applications 60/134,552, filed May 17, 1999, 60/135,851, filed May 24, 1999, 60/136,759, filed May 28, 1999, and 60/135,852, filed May 24, 1999. U.S. patent application Ser. No. 09/935,779 is also a continuation-in-part of U.S. patent application Ser. No. 09/315,026, filed May 20, 1999 (now U.S. Pat. No. 7,024,449), which receives the benefit of priority from provisional applications 60/134,552, filed May 17, 1999, 60/086,516, filed May 22, 1998, 60/086,588 filed May 22, 1998, 60/086,948, filed May 27, 1998, 60/087,587, filed Jun. 1, 1998, and 60/088,459, filed Jun. 8, 1998. U.S. patent application Ser. No. 09/935,779 is also a continuation-in-part of U.S. patent application Ser. No. 09/213,875, filed Dec. 17, 1998 (now U.S. Pat. No. 6,725,250), which receives the benefit of priority of provisional application 60/068,366, filed Dec. 19, 1997, and which is a continuation-in-part of U.S. patent application Ser. No. 08/980,058, filed Nov. 26, 1997 (now U.S. Pat. No. 6,732,141), which receives the benefit of priority of provisional application 60/066,415, filed Nov. 24, 1997, provisional application 60/066,313, filed Nov. 21, 1997, provisional application 60/033,871, filed Dec. 20, 1996, provisional application 60/032,207 filed Dec. 2, 1996, and provisional application 60/031,855, filed Nov. 29, 1996. U.S. patent application Ser. No. 09/315,026 is also a continuation-in-part of PCT application PCT/US98/27058, filed Dec. 17, 1998 and designating the United States. PCT/US98/27058 receives the benefit of provisional application 60/068,366, filed Dec. 19, 1997. U.S. patent application Ser. No. 09/315,026 is also a continuation-in part of PCT application PCT/US97/21812, filed Nov. 28, 1997 and designating the United States. PCT/US97/21812 receives the benefit of priority of provisional application 60/066,415, filed Nov. 24, 1997, provisional application 60/066,313, filed Nov. 21, 1997, provisional application 60/033,871, filed Dec. 20, 1996, provisional application 60/032,207, filed Dec. 2, 1996, and provisional application 60/031,855, filed Nov. 29, 1996. PCT/US97/21812 is a continuation-in-part of U.S. patent application Ser. No. 08/980,058, whose priority is discussed above. U.S. patent application Ser. No. 09/935,779 is also a continuation-in-part of U.S. patent application Ser. No. 09/085,755, filed May 27, 1998 (now U.S. Pat. No. 7,634,529), which receives the benefit of priority of provisional applications 60/066,313, filed Nov. 21, 1997, 60/066,415, filed Nov. 24, 1997, 60/068,366, filed Dec. 19, 1997, 60/086,588, filed May 22, 1998, and 60/086,516, filed May 22, 1998. U.S. patent application Ser. No. 09/085,755 is also a continuation-in-part of U.S. patent application Ser. No. 08/980,058 and PCT application PCT/US97/21812, whose respective priority is discussed above. U.S. patent application Ser. No. 09/935,779 is also a continuation-in-part of U.S. patent application Ser. No. 08/980,058, whose priority is discussed above. U.S. patent application Ser. No. 09/571,558 is also a continuation-in-part of U.S. patent application Ser. Nos. 09/085,755, 09/213,875, and 09/315,026, whose respective priority is discussed above. U.S. patent application Ser. No. 09/315,026 is also a continuation-in-part of U.S. patent application Ser. Nos. 09/085,755 and 09/213,875, whose respective priority is discussed above. The contents of all the above applications are incorporated herein in their entirety by reference.

BACKGROUND OF THE INVENTION

This invention relates generally to one or more computer networks that include computers, such as personal computers (PC's) or network computers such as servers, which have microprocessors linked by broadband transmission means and have hardware, software, firmware, and other means such that at least two parallel processing operations occur that involve at least two sets of computers in the network or in interconnected networks. This invention constitutes a form of metacomputing.

More particularly, this invention relates to one or more large networks, like the Internet, which comprise smaller networks and large numbers of interconnected computers, wherein multiple separate parallel or massively parallel processing operations involving multiple different sets of computers occur simultaneously. Even more particularly, this invention relates to one or more such networks wherein multiple parallel or massively parallel microprocessing processing operations occur separately or in an interrelated fashion, and wherein ongoing network processing linkages are established between virtually any microprocessors of separate computers connected to the network.

Still more particularly, this invention relates generally to a network structure or architecture that enables the shared use of network microprocessors for parallel processing, including massive parallel processing, and other shared processing such as multitasking, wherein personal computer owners provide microprocessor processing power to a network, such as for parallel or massively parallel processing or multitasking, in exchange for network linkage to other personal computers and other computers supplied by network providers such as Internet Service Providers (ISP's), including linkage to other microprocessors for parallel or other processing such as multitasking. The financial basis of the shared use between owners and providers may be whatever terms to which the parties agree, subject to governing laws, regulations, or rules, including payment from either party to the other based on periodic measurement of net use or provision of processing power like a deregulated electrical power grid or involving no payment. The network system may provide an essentially equivalent usage of computing resources by both users and providers since any network computer operated by either entity is potentially both a user and provider of computing resources alternately or simultaneously, assuming multitasking is operative. A user may have an override option exercised on the basis of, for example, a user profile, a user's credit line, or relatively instant payment.

This invention also relates to a network system architecture including hardware and software that provides use of the Internet or other network, without cost, to users of personal computers or other computers, while also providing users with computer processing performance that at least doubles every 18 months through metacomputing means. This metacomputing performance increase provided by the new Grid (or Metalnternet) is in addition to other performance increases, such as those already anticipated by Moore's Law.

The computer industry has been governed over the last 30 years by Moore's Law, which holds that the circuitry of computer chips shrinks substantially each year, yielding a new generation of chips every 18 months with twice as many transistors, such that microprocessor computing power effectively doubles every year-and-a-half.

The long-term trend in computer chip miniaturization is projected to continue unabated over the next few decades. For example, slightly more than a decade ago a 16 kilobit DRAM (dynamic random access memory) memory chip (storing 16,000 data bits) was typical; the standard in 1996 was the 16 megabit chip (16,000,000 data bits), which was introduced in 1993; industry projections are for 16 gigabit memory chips (16,000,000,000 data bits) to be introduced in 2008 and 64 gigabit chips in 2011; and 16 terabit chips (16,000,000,000,000 data bits) may be conceivable by the mid-to-late 2020's, by which time such microchips may have become nanochips in terms of their circuit dimensions. This is a thousand-fold increase regularly every fifteen years. Hard drive speed and capacity are also growing at a spectacular rate, even higher in recent years than that of semiconductor microchips.

Similarly, regular and enormous improvements may continue in microprocessor computing speeds, whether measured in simple clock speed or MIPS (millions of instructions per second) or numbers of transistors per chip. For example, performance has improved by four or five times every three years since Intel launched its X86 family of microprocessors used in the currently dominant âWintelâ standard personal computers. The initial Intel Pentium Pro microprocessor was introduced in 1995 and is a thousand times faster than the first IBM standard PC microprocessor, the Intel 8088, which was introduced in 1979. By 1996 the fastest of microprocessors, such as Digital Equipment Corporation's Alpha chip, and even the microprocessor of the Nintendo 64 video game system, were faster than the processor in the original Cray Y-MP supercomputer.

Microprocessors, software, firmware, and other components are also evolving from 8-bit and 16-bit systems into the 32-bit systems that are becoming the standard today, with some 64-bit systems like the DEC Alpha already introduced and more coming, such as Intel's Itanium microprocessor in 2001, with future increases to 128-bit systems likely.

A second major development trend in the past decade or so has been the rise of parallel processing, a computer architecture utilizing more than one CPU microprocessor linked together into a single computer with new operating systems having modifications that allow such an approach. Thousands of relatively simple microprocessors may be used together for massively parallel processing. The field of supercomputing has been overtaken by this approach, which includes designs utilizing many identical standard personal computer microprocessors.

Hardware, firmware, software, and other components specific to parallel processing are in a relatively early stage of development compared to that for single processor computing. Therefore, much further design and development are expected in the future to better maximize the computing capacity made possible by parallel processing. Continued improvement is anticipated in system hardware, software, and architectures for parallel processing so that reliance on the need for multiple microprocessors to share a common central memory is reduced, thereby allowing more independent operation of those general purpose microprocessors, each with their own discrete memory, like current personal computers, workstations, and most other computer systems architecture. For unconstrained operation, each individual microprocessor should have rapid access to sufficient memory.

Several models of personal computers having more than one general purpose microprocessor are now available. In the future, personal computers, broadly defined to include versions not currently in use, will likely also employ parallel computing utilizing multiple microprocessors or massively parallel computing with very large numbers of microprocessors. Future designs, such as Intel's Itanium chip, are expected to have a significant number of parallel processors on a single microprocessor chip.

A form of parallel processing called superscalar processing is also being employed within microprocessor design. The current generation of microprocessors, such as the Intel Pentium, have more than one data path within the microprocessor in which data is processed, with two to three paths being typical now and as many as eight in 1998 in IBM's new Power 3 microprocessor chip.

A third major development trend is the increasing size of bandwidth, which is a measure of communications power or transmission speed, in terms of units of data per second, between computers connected by a network. Previously, the local area networks and telephone lines typically linking computers including personal computers have operated at speeds much lower than the processing speeds of a personal computer. For example, a typical 1997 Intel Pentium operates at 100 MIPS, whereas the most common current Ethernet connecting PC's is roughly 10 times slower at 10 megabits per second (Mbps), although some Ethernet connections are now 100 Mbps and telephone lines are very much slower, the highest typical speed in 1998 being the approximately 56 kilobits reachedduring downloads.

The situation is expected to change dramatically. Bandwidth or transmission speed is anticipated to expand from 5 to 100 times as fast as the rise of microprocessor speeds, due to the use of coaxial cable, wireless, and especially fiber optic cable and optical wireless, instead of old telephone twisted pair lines, and due to the use of wideband communication such as dense wave division multiplexing (DWDM) and wideband code division multiple access (CDMA), as well as ultrawideband wireless. In DWDM systems, multiple channels are transmitted over a single fiber because they are sent at different wavelengths. Telecommunication providers are now making available single fiber connections supporting a bandwidth of 40 gigabits per single fiber, and, alternatively, as many as 160 wavelength channels (lambdas) per single fiber. In CDMA systems, users are multiplexed across the same spectrum, with each user being assigned a different instance of a noise-like carrier wave.

BACKGROUND OF THE INVENTION

Technical improvements are expected in the near term which will make it possible to carry over 2 gigahertz (billions of cycles per second) on each of 700 wavelength channels (lambdas), adding up to more than 1,400 gigahertz on a single fiber thread. Experts have estimated that the bandwidth of optical fiber has been utilized one million times less fully than the bandwidth of coaxial or twisted pair copper lines. Within a decade, 10,000 wavelength streams per fiber are expected; 20 to 80 wavelengths on a single fiber is already commercially available. The use of thin mirrored hollow wires or tubes called omniguides may also provide very substantial additional increases.

Other network connection developments, such as asynchronous transfer mode (ATM) and digital signal processors, whose price/performance ratio has improved tenfold every two years, are also supporting the rapid increase in bandwidth. The increase in bandwidth reduces the need for switching, and switching speed will be greatly enhanced when practical optical switches are introduced in the near future, potentially reducing costs substantially.

The result of this huge bandwidth increase is extraordinary: already it is technically possible to connect virtually any computer to a network with a bandwidth that equals or exceeds the computer's own internal system bus speed, even as that bus speed itself is increasing significantly. The principal constraint is the infrastructure, consisting mostly of connecting the âlast mileâ to personal computers with optical fiber or other broad bandwidth connections, which still need to be built. The system bus of a computer is its internal network connecting many or most of its internal components such as microprocessor, random access memory (RAM), hard drive, modem, floppy drive, and CD-ROM; for recent personal computers, the system bus has been only about 40 megabits per second, but is up to 133 megabits per second on Intel's Pentium PCI bus in 1995. IBM's 1998 Power3 microprocessor chip has a system bus of 1.6 gigabits per second and there is now up to a gigabit per second on Intel's Pentium PCI bus.

Despite these tremendous improvements anticipated in the future, a typical PC is already so fast that its microprocessor is essentially idle during most of the time the PC is in actual use, and the operating time itself is but a small fraction of those days the PC is even in use at all. Nearly all PC's are essentially idle during roughly all of their useful life. A microprocessor of a PC may be in an idle state 99.9% of the time, disregarding unnecessary microprocessor busywork such as executing screen saver programs, which have been made essentially obsolete by power-saving CRT monitor technology, which is now standard in the PC industry.

Because the reliability of PC's is so exceptionally high now, with the mean time to failure of all components typically several hundred thousand hours or more, the huge idle time of PC's represents a total loss; given the high capital and operating costs of PC's, the economic loss is very high. PC idle time does not in effect store a PC, saving it for future use, since the principle limiting factor to continued use of today's PC's is obsolescence, not equipment failure resulting from use.

Moreover, there is continuing concern that Moore's Law, which holds that the constant miniaturization of circuits results in a doubling of computing power every 18 months, cannot continue to hold true much longer. Indeed, Moore's Law may now be nearing its limits for silicon-based devices, perhaps by as early as 2010. No new technologies have yet emerged that seem to have the potential for development to a practical level by then, although many recent advances have the potential to maintain Moore's Law.

SUMMARY OF THE INVENTION

However, the confluence of all three of the established major trends summarized above-supercomputer-like personal computers, the spread of parallel processing using personal computer general purpose microprocessors (particularly massively parallel processing), and the enormous increase in network communications bandwidth-enables a solution to the excessive idleness problem of personal computers and the possible end of Moore's Law. The solution may achieve very high potential economic savings once the basic infrastructure connecting personal computers with optical fiber is in place in the relatively near future.

The solution is to use those mostly idle PC's (or their equivalents or successors) to build a parallel or massively parallel processing computer or computers utilizing a very large network, like the Internet or, more specifically, like the World Wide Web (WWW), or their equivalents or eventual successors like the Grid or Metalnternet (and including Internet II and the Next Generation Internet, which are under development now and which will utilize much broader bandwidth and will coexist with the Internet, the structure of which is in ever constant hardware and software upgrade and including the Superinternet based on essentially all optical fiber transmission) with extremely broad bandwidth connections and virtually unlimited data transmission speed.

A prime characteristic of the Internet is the very large number of computers of all sorts already linked thereto, with the future potential for an effectively universal connection. The Internet is a network of networks of computers that provides nearly unrestricted access worldwide. The currently existing and soon-to-be widely available very broad bandwidth of network communications is used to link personal computers externally in a manner at least equivalent to, and probably much faster than, the faster internal system buses of the personal computers, so that no external processing constraint is imposed on linked personal computers by data input, output, or throughput; the speed of the microprocessor itself and the internal connections or buses of the PC are the only processing constraint of the system.

This makes possible efficient external parallel processing (and multitasking), including massively parallel processing, in a manner paralleling more conventional internal parallel processing, called superscalar processing.

In one embodiment, the World Wide Web is transformed into a huge virtual massively parallel processing computer or computers, with potential through its established hyperlinks connections to operate in a manner at least somewhat like a neural network or neural networks, since the speed of transmission in the broadband linkages is so great that any linkage between two microprocessors is virtually equivalent to direct, physically close connections between those microprocessors.

With further development, digital signal processor-type microprocessors and/or analogue microprocessors may be particularly advantageous for this approach, either alone or in conjunction with conventional microprocessors and/or the new microprocessors described below. Networks with WWW-type hyperlinks incorporating digital signal processor-type microprocessors could operate separately from networks of conventional microprocessors or with one or more connections between such differing networks or with relatively complete integration between such differing networks. Simultaneous operation across the same network connection structure should be possible, employing non-interfering transmission links.

Such extremely broad bandwidth networks of computers enable every PC within the network to be fully utilized or nearly so. Because of the extraordinary extent to which existing PC's are currently idle, at optimal performance this new system may result in a thousand-fold increase in computer power available to each and every PC user, and, on demand, almost any desired level of increased power, limited mostly by increased cost, which however are relatively far less than possible from other conceivable computer network configurations. This revolutionary increase is in addition to the extremely rapid, but evolutionary increases already occurring in the computer/network industry, as discussed above.

The metacomputing hardware and software means of the Grid (or Metalnternet) provides performance increases that are likely to at least double every eighteen months based on the doubling of personal computers shared in a typical parallel processing operation by a standard PC user, starting first with at least 2 PC's, then about 4, about 8, about 16, about 32, about 64, about 128, about 256, and about 512, for example. After about fifteen years, for example, it is anticipated that each standard PC user will likely be able to use a maximum of about 1,024 personal computers for parallel processing or any other shared computing use, while generally using for free the Internet or its successors, like the Grid (or Metalnternet). At the other end of the performance spectrum, supercomputers experience a similar performance increase generally, but ultimately the performance increase is limited primarily by the cost of adding network linkages to available PC's, so there is definite potential for a huge leap in supercomputer performance.

Network computer systems as described above offer almost limitless flexibility due to the abundant supply of heretofore idle connected microprocessors. This advantage allows âtightly coupledâ computing problems, which normally are difficult to process in parallel, to be solved without knowing in advance how many processors are available (as is now necessary in relatively massively parallel processing), what they are, and their connection characteristics. A minimum number of equivalent processors (with equivalent other specifications) are easily found nearby in a massive network like the Internet and assigned within the network from those multitudes available nearby. Moreover, the number of microprocessors used are almost completely flexible, depending on the complexity of the problem, and limited only by cost. The existing problem of time delay is solved largely by the widespread introduction of broad bandwidth connections between computers processing in parallel.

The state of the known art relating to this application is summarized in The Grid: Blueprint for a New Computing Infrastructure , edited by Ian Foster and Carl Kesselman, and published by Morgan Kaufman Publishers, Inc. in 1998. The state of the known art relating to this application is also summarized in: Scalable Parallel Computing by Kai Hwang and Zhiwei Xu, published by WCB McGraw-Hill in 1998 ; Parallel Programming by Barry Wilkinson and Michael Allen, published by Prentice Hall in 1998 ; Computer Architecture: A Quantitative Approach (2nd Edition) by David Patterson and John Hennessy, published by Morgan Kaufmann in 1996 ; Parallel Computer Architecture by David Culler and Jaswinder Singh, published by Morgan Kaufman in 1998; and Computer Organization and Design by John Hennessy and David Patterson, published by Morgan Kaufman in 1998.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a simplified diagram of a section of a computer network, such as the Internet, showing an embodiment of a meter means which measures flow of computing during a shared operation such as parallel processing between a typical PC user and a network provider.

FIG. 2 is a simplified diagram of a section of a computer network, such as the Internet, showing an embodiment of another meter means which measures the flow of network resources, including shared processing, being provided to a typical PC user and a network provider.

FIG. 3 is a simplified diagram of a section of a computer network, such as the Internet, showing an embodiment of another meter means which, prior to execution, estimates the level of network resources, and their cost, of a shared processing operation requested by a typical PC user from a network provider.

FIGS. 4A-4C are simplified diagrams of a section of a computer network, such as the Internet, showing in a sequence of steps an embodiment of a selection means whereby a shared processing request by a PC is matched with a standard preset number of other PC's to execute a shared operation.

FIGS. 5A and 5B are simplified diagrams of a section of a computer network, such as the Internet, showing embodiments of a control means whereby the PC, when idled by its user, is made available to the network for shared processing operations.

FIG. 6 is a simplified diagram of a section of a computer network, such as the Internet, showing an embodiment of a signal means whereby the PC, when idled by its user, signals its availability to the network for shared processing operations.

FIG. 7 is a simplified diagram of a section of a computer network, such as the Internet, showing an embodiment of a receiver and/or interrogator means whereby the network receives and/or queries the availability for shared processing status of a PC within the network.

FIG. 8 is a simplified diagram of a section of a computer network, such as the Internet, showing an embodiment of a selection and/or utilization means whereby the network locates available PC's in the network that are located closest to each other for shared processing.

FIG. 9 is a simplified diagram of a section of a computer network, such as the Internet, showing an embodiment of a system architecture for conducting a request imitated by a PC for a search using parallel processing means that utilizes a number of networked PC's.

FIGS. 10A-10Q are simplified diagrams of a section of a computer network, such as the Internet, showing an embodiment of a system architecture utilizing an internal firewall to separate that part of a networked PC (including a system reduced in size to a microchip) that is accessible to the network for shared processing from a part that is kept accessible only to the PC user; also showing the alternating role that each PC in the network may play as either a master or slave in a shared processing operation involving one or more slave PC's in the network; and showing a home or business network system which can be configured as an Intranet; in addition, showing PC and PC microchips controlled by a controller (including remote) with limited or no processing capability; and showing PC and PC microchips in which an internal firewall 50 can be reconfigured by a PC user.

FIG. 11 is a simplified diagram of a section of a computer network, such as the Internet, showing an embodiment of a system architecture for connecting clusters of PC's to each other by wireless means, to create the closest possible (and therefore fastest) connections.

FIG. 12 is a simplified diagram of a section of a computer network, such as the Internet, showing an embodiment of a system architecture for connecting PC's to a satellite by wireless means.

FIG. 13 is a simplified diagram of a section of a computer network, such as the Internet, showing an embodiment of a system architecture providing a cluster of networked PC's with complete interconnectivity by wireless means.

FIG. 14A is a simplified diagram of a section of a computer network, such as the Internet, showing an embodiment of a transponder means whereby a PC can identify one or more of the closest available PC's in a network cluster to designate for shared processing by wireless means. FIG. 14B shows clusters connected wirelessly. FIG. 14C shows a wireless cluster with transponders and with a network wired connection to the Internet. FIG. 14D shows a network client/server wired system with transponders.

FIG. 15 is a simplified diagram of a section of a computer network, such as the Internet, showing an embodiment of a routing means whereby a PC request for shared processing is routed within a network using broad bandwidth connection means to another area in a network with one or more idle PC's available.

FIGS. 16A-16Z, 16AA, and 16AB show a new hierarchical network architecture for personal computers and/or microprocessors based on subdivision of parallel processing or multi-tasking operations through a number of levels down to a processing level.

FIGS. 17A-17D show an internal firewall 50 with a dual function, including that of protecting Internet users (and/or other network users sharing use) of one or more slave personal computers PC 1 or microprocessors 40 from unauthorized surveillance or intervention by an owner/operator of those slave processors.

FIGS. 18A-18D show designs for one or more virtual quantum computers integrated into one or more digital computers.

FIG. 19 shows special adaptations to allow the use of idle automobile computers to be powered and connected to the Internet (or other net) for parallel or multi-tasking processing.

FIGS. 20A and 20B show separate broad bandwidth outputs or inputs such as an optical connection like glass fiber from each microprocessor

40 or 94 .

FIGS. 21A and 21B are similar to FIGS. 20A and 20B , but show additionally that all microprocessors of a personal computer or personal computer on a microchip can have a separate input/output communication link to a digital signal processor (DSP) or other transmission/reception connection component. FIG. 21C shows a H-tree configuration of binary tree networks.

FIGS. 22A-22C shows a PC microprocessor on a microchip similar to that of FIG. 21B , except that FIGS. 22A- 22C

show microprocessors

93 and 94 each connecting to an optical wired connection 99 â² such as thin mirrored hollow wire or optical omniguide or optical fiber.

FIGS. 23A-23E show multiple firewalls 50 within a personal computer 1 or PC microchip 90 .

FIG. 24 shows a hard drive with an internal firewall 50 .

FIGS. 25A-25D show the use for security of power interruption or data overwrite of volatile memory like DRAM and non-volatile memory like Flash or MRAM (or ovonics), respectively, of the network portion of a personal computer PCI or system on a microchip PC 90 .

FIGS. 26A-26C show exemplary microchip and photovoltaic cell embodiments.

FIGS. 27A-27H show exemplary microchip and Faraday Cage embodiments.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiments useful for a network of computers are presented. In an embodiment, an apparatus includes a microchip and a Faraday Cage. The microchip includes a personal computer with a general purpose microprocessor on the microchip. The Faraday Cage surrounds at least a portion of the microchip. In another embodiment, an apparatus includes a microchip. The microchip includes a general purpose microprocessor and one or more photovoltaic cells.

The new network computer utilizes PC's as providers of computing power to the network, not just users of network services. These connections between network and personal computer are enabled by a new form of computer/network financial structure that is rooted in the fact that economic resources being provided the network by PC owners (or leaser) are similar in value to those being provided by the network provider providing connectivity.

Unlike existing one-way functional relationships between PC users and network providers such as internet service providers, which often currently utilize telecommunications networks for connectivity, wherein the network provider provides access to a network like the Internet for a fee, much like cable TV services, this new relationship recognizes that the PC user is also providing the network access to the user's PC for parallel computing use, which has a similar value. The PC thus both provides and uses services on the network, alternatively or potentially even virtually simultaneously, in a multitasking mode.

This new network operates with a structural relationship that is roughly like that which presently exists between an electrical power utility and a small independent power generator connected to a deregulated utility's electrical power grid, wherein electrical power can flow in either direction between utility and independent generator depending on the operating decisions of both parties, and at any particular point in time each party is in either a debt or credit position relative to the other based on the net direction of that flow for a given period, and each party is billed accordingly. In the increasingly deregulated electrical power industry, electrical power, in terms of creation and transmission, is becoming a commodity bought and sold in a competitive marketplace that crosses traditional borders. With the structural relationship proposed herein for the new network, parallel free market structures can develop over time in a new computer power industry dominated by networks of personal computers in all their forms providing shared processing in a grid scaling almost seamlessly from local to national to international like an open market electrical power grid.

For this new network and its structural relationships, a network provider or Internet service provider (ISP) is defined in the broadest possible way as any entity (corporation or other business, government, not-for-profit, cooperative, consortium, committee, association, community, or other organization or individual) that provides personal computer users (very broadly defined below) with initial and continuing connection hardware and/or software and/or firmware and/or other components and/or services to any network, such as the Internet and WWW or Internet II or Next Generation Internet (NGI) or their present or future equivalents, coexistors, or successors, like the herein proposed Grid (or Metalnternet), including any of the current or future types of Internet access providers (ISP's) including telecommunication companies, television cable or broadcast companies, electrical power utilities or other related companies, satellite communications companies, or their present or future equivalents, coexistors or successors.

The connection means used in the networks of the network providers, including between personal computers or equivalents or successors, may be very broad bandwidth, including electromagnetic connections and optical connections, including wired like fiber optic cable or wireless like optical wireless, for example, but not excluding any other electromagnetic or other means, including television coaxial cable and telephone twisted pair, as well as associated gateways, bridges, routers, and switches with all associated hardware and/or software and/or firmware and/or other components and their present or future equivalents or successors. The computers used by the Internet service providers include any current or future computers, including such current examples as mainframes, minicomputers, servers, and personal computers, and their associated hardware and/or software and/or firmware and/or other components, and their present or future equivalents or successors.

Other levels of network control beyond the Internet or other network service provider also exist to control any aspect of the parallel processing network structure and function, any one of which levels may or may not control and interact directly with the PC user. For example, at least one level of network control like the World Wide Web Consortium (W3C) or Internet Society (ISOC) or other ad hoc industry consortia establish and ensure compliance with any prescribed parallel processing network standards and/or protocols and/or industry standard agreements for any hardware and/or software and/or firmware and/or other component connected to the network. Under the consensus control of these consortia/societies, other levels of the parallel processing network control can deal with administration and operation of the network. These other levels of the parallel processing network control can potentially be constituted by any network entity, including those defined immediately above for network providers.

The principal defining characteristic of the parallel processing network herein described is communication connections (including hardware and/or software and/or firmware and/or other component) of any form, including electromagnetic (such as radio or microwaves and including light) and electrochemical (and not excluding biochemical or biological), between PC users and their computers, with connection (either directly or indirectly) to the largest number possible of users and their computers and microprocessors being highly advantageous, such as networks like the Internet (and Internet II and the Next Generation Internet) and WWW and equivalents and successors, like the Grid (or Metalnternet). Multiple levels of such networks will likely coexist with different technical capabilities, like Internet and Internet II, but have interconnection and therefore communicate freely between levels, for such standard network functions as electronic mail, for example.

A personal computer (PC) user is defined in the broadest possible way as any individual or other entity routinely using a personal computer, which is defined as any computer, such as digital or analog or neural or quantum, particularly including personal use microprocessor-based personal computers having one or more general purpose microprocessors (each including one or more parallel processors) in their general current form, including hardware with fixed or reconfigurable circuitry (such as field-programmable gate array or FPGA) and/or electromechanical components (including micro or nano sized) and/or optical components, including all-optical, and/or software and/or firmware and/or any other component and their present and future equivalents or successors, such as application-specific (or several application) computers, network computers, handheld personal digital assistants, personal communicators such as telephones and pagers, wearable computers, digital signal processors, neural-based computers (including PC's), entertainment devices such as televisions and associated cable digital set-top control boxes, video tape recorders, video electronic games, videocams, compact or digital video disk (CD or DVD) player/recorders, radios and cameras, other household electronic devices, business electronic devices such as printers, copiers, fax machines, footwear, automobile or other transportation equipment devices, robots, toys, and other electronic devices, especially including those owned (or leased directly or indirectly) and used directly by individuals, utilizing one or more microprocessors, including those made of inorganic compounds such as silicon and/or other inorganic or organic (including biological, such as DNA) compounds, and other current or successor devices incorporating one or more microprocessors (or functional or structural equivalents), including routers, switches, and other network devices, as well as current and future forms of mainframe computers, minicomputers, workstations, and even supercomputers, as well as routers, switches, and other electrical or optical network devices (or microelectro-mechanical devices such as MEMS), that can be considered as PCs in the distributed processing network described herein, since they can be used functionally in the same general way in the network as a PC or a PC can be used to perform their functions, at least in a limited fashion alone or more effectively in numbers that are aggregated together or distributed. Such personal computers as defined above have owners or Teasers, which may or may not be the same as the computer users. Continuous connection of computers to the network, such as the Internet, WWW, or equivalents or successors, is not required, since connection can also be made at the initiation of a shared processing operation.

Parallel processing is defined as one form of shared processing involving two or more microprocessors used in solving the same computational problem or other task. Massively parallel microprocessor processing involves large numbers of microprocessors. In today's technology, massive parallel processing is probably to be considered to be about 64 microprocessors (referred to in this context as nodes) and over 7,000 nodes have been successfully tested in an Intel supercomputer design using PC microprocessors (Pentium Pros). It is anticipated that continued software improvements will make possible effective use of a much larger number of nodes, very possibly limited only by the number of microprocessors available for use on a given network, even an extraordinarily large one like the Internet or its equivalents and/or successors, like the Grid (or Metalnternet). Shared processing also includes multitasking, which is unrelated processing in parallel.

Broadband wavelength or broad bandwidth network transmission is defined here to mean a transmission speed (usually measured in bits per second) that is at least high enough (or roughly at least equivalent to the internal clock speed of the microprocessor or microprocessors times the number of microprocessor channels equaling instructions per second or operations per second or calculations per second) so that the processing input and output of the microprocessor is substantially unrestricted, particularly including at peak processing levels, by the bandwidth of the network connections between microprocessors that are performing some form of parallel processing, particularly including massive parallel processing. Since this definition is dependent on microprocessor speed, it increases as microprocessor speeds increase. For microchips with more than one processor, the network connection to the microchip may have bandwidth broad enough to ensure that all of the microprocessors are unrestricted by a bottleneck at the connection during the microprocessors' peak processing levels.

However, a connection means referenced above is a light wave or optical waveguide connection such as fiber optic cable, which in 1996 already provided multiple gigabit bandwidth on single fiber thread and is rapidly improving significantly on a continuing basis, so the general use of optical waveguide connections such as fiber between PCs may assure broad bandwidth for data transmission that is far greater than microprocessor and associated internal bus speed to provide data to be transmitted. In addition, new wired optical connections or waveguide in the form of thin, mirrored hollow wires or tubes called omniguides offer even much greater bandwidth than optical fiber and without need for amplification when transmitting over distances, unlike optical fiber. The connection means to provide broad bandwidth transmission is either wired or wireless, with wireless (especially optical) generally provided for mobile personal computers (or equivalents or successors) and as otherwise indicated below. Wireless connection bandwidth is also increasing rapidly and optical wireless bandwidth is considered to offer essentially the same benefit as fiber optic cable: data transmission speed that exceeds data processing speed.

The financial basis of the shared use between owners/leasers and providers is whatever terms to which the parties agree, subject to governing laws, regulations, or rules, including payment from either party to the other based on periodic measurement of net use or provision of processing power, in a manner like an deregulated or open market electrical power grid.

In one embodiment, as shown in FIG. 1 , in order for this network structure to function effectively, there is a meter device 5 (comprising hardware and/or software and/or firmware and/or other component) to measure the flow of computing power between PC 1 user and network 2 provider, which may provide connection to the Internet and/or World Wide Web and/or Internet II and/or any present or future equivalent or successor 3 , like the Grid (or Metalnternet). In one embodiment, the PC user may be measured by some net rating of the processing power being made available to the network, such as net score on one or more standard tests measuring speed or other performance characteristics of the overall system speed, such as PC Magazine's benchmark test program, ZD Winstone (potentially including hardware and/or software and/or firmware and/or other component testing) or specific individual scores for particularly important components like the microprocessor (such as MIPS or millions of instructions per second) that may be of application-specific importance, and by the elapsed time such resources were used by the network. In the simplest case, for example, such a meter need measure only the time the PC was made available to the network for processing 4 , which can be used to compare with time the PC used the network (which is already normally measured by the provider, as discussed below) to arrive at a net cost; potential locations of such a meter include at a network computer such as a server, at the PC, and at some point on the connection between the two. Throughput of data in any standard terms is another potential measure.

In another embodiment, as shown in FIG. 2 , there also is a meter device 7 (comprised of hardware and/or software and/or firmware and/or other component) that measures the amount of network resources <b

CLAIMS

Claims ( 19 )

What is claimed is:

1. A computer or microchip, comprising:

a master controlling microprocessor and firmware of the computer or microchip,

an internal hardware firewall located between a protected portion of the computer or microchip that is protected by the internal hardware firewall and a network portion of the computer or microchip, the network portion having a connection for a network of computers including the World Wide Web and/or the Internet; the internal hardware firewall denies access to at least the protected portion of the computer or microchip from the network; and

network communications devices located in the network portion of the computer or microchip; and

one or more or at least two or four or eight or 16 or 32 or 64 or 128 or 256 or 512 or 1024 microprocessors or processing units, each with associated random access memory (RAM), that are not network communications devices, wherein the one or more microprocessors or processing units and random access memory (RAM) are located in the network portion of the computer or microchip and are separate from the internal hardware firewall; and

wherein a location of the internal hardware firewall permits unrestricted access by the network of computers to the network portion of the computer or microchip so that processing operations other than network communications and firewall operations conducted by the computer or microchip with the network of computers are executed by one or more of the microprocessors or processing units and random access memory (RAM) in the network portion of the computer or microchip: and

wherein the master controlling microprocessor and at least a part of the firmware are located in the protected portion of the computer or microchip and the master controlling microprocessor has preemptive control of the one or more microprocessors or processing units and associated random access memory (RAM) in the network portion of the computer or microchip, and

the preemptive control including erasure of at least a part of the random access memory (RAM) associated with at least one of the one or more microprocessors or processing units in the network portion of the computer or microchip prior to use of the network portion of the computer or microchip by a user or operating system of the computer or microchip.

2. The computer or microchip of claim 1 , wherein the firmware located in the protected portion of the computer or microchip includes at least a system BIOS.

3. The computer or microchip of claim 1 , wherein the firmware located in the protected portion of the computer or microchip includes at least the operating system kernel.

4. The computer or microchip of claim 1 , wherein each of the one or more microprocessors or processing units and/or associated random access memory (RAM) in the network portion is protected by its own internal hardware firewall.

5. The computer or microchip of claim 1 , wherein the preemptive control includes erasure of all of the random access memory (RAM) associated with at least one of the one or more microprocessors or processing units in the network portion of the computer or microchip prior to the use of the network portion of the computer or microchip by the user or the operating system of the computer or microchip.

6. The computer or microchip of claim 1 , wherein all or part of the random access memory (RAM) associated with the one or more microprocessors or processing units in the network portion is erased prior to network use of the network portion of the computer or microchip.

7. The computer or microchip of claim 1 , wherein the erasure of the part of the random access memory (RAM) associated with at least one of the one or more microprocessors or processing units in the network portion is by the user or by the operating system.

8. The computer or microchip of claim 2 , wherein the erasure of all of the random access memory (RAM) associated with the one or more microprocessors or processing units in the network portion is by the user or by the operating system.

9. The computer or microchip of claim 2 , wherein all or part of the random access memory (RAM) associated with the one or more microprocessors or processing units in the network portion is volatile memory and is erased by power interruption to the random access memory (RAM).

10. The computer or microchip of claim 2 , wherein all or part of the random access memory (RAM) in the network portion is non-volatile memory and is erased by overwriting the random access memory (RAM).

11. The computer or microchip of claim 2 , wherein the computer or microchip includes one or more or at least two or four or eight or 16 or 32 or 64 or 128 or 256 or 512 or 1024 additional internal firewalls, each protecting a microprocessor or processing unit with an integrated random access memory (RAM).

12. The computer or microchip of claim 2 , wherein the protected portion of the computer or microchip includes random access memory (RAM) protected by one or more additional internal firewalls.

13. The computer or microchip of claim 2 , wherein the protected portion and/or the network portion of the computer or microchip include one or more additional internal firewalls.

14. The computer or microchip of claim 1 , wherein all of the firmware is located in the protected portion of the computer or microchip.

15. A computer or microchip comprising:

a master controlling device microprocessor and firmware of the computer or microchip,

network communications devices located in the network portion of the computer or microchip; and

one or more or at least two or four or eight or 16 or 32 or 64 or 128 or 256 or 512 or 1024 microprocessors or processing units, each with associated random access memory (RAM) that are not network communications devices, wherein the one or more microprocessors or processing units and random access memory (RAM) are located in the network portion of the computer or microchip and are separate from the internal hardware firewall; and

the preemptive control including erasure of the random access memory (RAM) associated with at least one of the one or more microprocessors or processing units in the network portion of the computer or microchip prior to use of the network portion of the computer or microchip by a user or operating system of the computer or microchip, and wherein at least a portion of the computer or microchip is surrounded by a first Faraday Cage.

16. The computer or microchip of claim 15 , wherein the computer or microchip is surrounded by a second Faraday Cage.

17. The computer or microchip of claim 15 , wherein all of the firmware is located in the protected portion of the computer or microchip.

18. A computer or microchip, comprising:

a master controlling microprocessor and firmware of the computer or microchip,

network communications devices located in the network portion of the computer or microchip; and

each of the one or more microprocessors or processing units and/or associated random access memory (RAM) is protected by its own internal hardware firewall that is also preemptively controlled by the master controlling microprocessor.

19. The computer or microchip of claim 18 , wherein all of the firmware is located in the protected portion of the computer or microchip.

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1996-11-29

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Expired - Fee Related

US9531671B2

( en )

Priority Applications (1)

Application Number

Priority Date

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US14/661,521

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1996-11-29

2015-03-18

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2019-06-10

2022-08-30

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Intranet access method, system and related device

US12525242B2

( en )

2021-11-11

2026-01-13

Sorenson Ip Holdings, Llc

Transcription presentation

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