ABSTRACT
Abstract
A method of manufacturing an electronic device, including: a) forming a plurality of chips, each including a plurality of connection areas and at least one first pad; b) forming a transfer substrate including, for each chip, a plurality of connection areas and at least one second pad, one of the first and second pads being a permanent magnet and the other one of the first and second pads being either a permanent magnet or made of a ferromagnetic material; and c) affixing the chips to the transfer substrate to connect the connection areas of the chips to the connection areas of the transfer substrate, by using the magnetic force between the pads to align the connection areas of the chips with the corresponding connection areas of the transfer substrate.
Description
This Application is a national stage filing under 35 U.S.C. § 371 of International Patent Application Serial No. PCT/FR2018/051137, filed May 4, 2018, which claims priority to French patent application FR17/54045, filed May 9, 2017, the contents of these applications are incorporated herein by reference in their entirety.
BACKGROUND
The present application concerns the forming of an emissive image display device comprising light-emitting diodes (LEDs), for example, a screen for a television, a computer, a smart phone, a tablet, etc.
DISCUSSION OF THE RELATED ART
A method of manufacturing an image display device comprising a plurality of elementary electronic microchips arranged in an array on a same transfer substrate has already been provided, in French patent application No. 1561421 filed on Nov. 26, 2015. According to this method, the microchips and the transfer substrate are manufactured separately. Each microchip comprises a stack of a LED and of a circuit for controlling the LED. The control circuit comprises a connection surface opposite to the LED, comprising a plurality of electric connection areas intended to be connected to the transfer substrate for the control of the microchip. The transfer substrate comprises a connection surface comprising, for each microchip, a plurality of electric connection areas intended to be respectively connected to the electric connection areas of the microchip. The chips are then placed on the transfer substrate, with their connection surfaces facing the connection surface of the transfer substrate, and affixed to the transfer substrate to connect the electric connection areas of each microchip to the corresponding electric connection areas of the transfer substrate.
It would be desirable to be able to at least partly improve certain aspects of this method.
In particular, due to the relatively small dimensions of the microchips, and given that each microchip comprises a plurality of separate electric connection areas, the alignment of the electric connection areas of the microchips with the corresponding electric connection areas of the transfer substrate is relatively difficult to achieve. It would be desirable to ease the implementation of such an alignment and/or to improve the obtained alignment accuracy.
SUMMARY
Thus, an embodiment provides an electronic device manufacturing method, comprising the steps of:
a) forming a plurality of chips, each comprising:
a plurality of electric connection areas arranged on a connection surface of the chip, and at least one first pad arranged in the vicinity of the chip connection surface;
b) forming a transfer substrate comprising, for each chip:
a plurality of electric connection areas arranged on a connection surface of the transfer substrate, and at least one second pad arranged in the vicinity of the connection surface of the transfer substrate, one of the first and second pads being a permanent magnet and the other one of the first and second pads being either a permanent magnet or made of a ferromagnetic material; and
c) affixing the chips to the transfer substrate by direct bonding to electrically connect the electric connection areas of each chip to the corresponding electric connection areas of the transfer substrate, by using the magnetic force between the first and second pads to align the electric connection areas of the chips with the corresponding electric connection areas of the transfer substrate.
According to an embodiment, in each chip, the first pad emerges on the side of the connection surface of the microchip.
According to an embodiment, in each chip, the first pad is buried under the connection surface of the chip.
According to an embodiment, in each chip, the connection surface of the chip is planar, the electric connection areas of the chip being flush with an external surface of a passivation layer of the chip.
According to an embodiment, the second pads emerge on the side of the connection surface of the transfer substrate.
According to an embodiment, the second pads are buried under the connection surface of the transfer substrate.
According to an embodiment, the connection surface of the transfer substrate is planar, the electric connection areas of the transfer substrate being flush with an external surface of a passivation layer of the transfer substrate.
According to an embodiment, the electric connection areas of the transfer substrate protrude from the connection surface of the transfer substrate.
According to an embodiment:
at the end of step a), the chips are arranged on a support substrate with a pitch between chips smaller than the pitch between chips of the final display device; and
at step c), a plurality of chips are selectively separated from the support substrate at the pitch of the final display device and affixed to the transfer substrate at this same pitch.
According to an embodiment:
at the end of step a), the chips are only laid, with no bonding, on the support substrate; and
at step c), the transfer substrate is brought above the chips, with its connection surface facing the connection surfaces of the chips, to simultaneously collect a plurality of chips at the pitch of the final display device.
According to an embodiment, the support substrate comprises cavities having the chips arranged therein so that the chips are laterally maintained by the cavity walls.
According to an embodiment, the bottom of each cavity of the support substrate is non-planar.
According to an embodiment, each chip comprises a stack of a LED and of an active circuit for controlling the LED.
Another embodiment provides an emissive display device comprising LEDs formed by a method such as defined hereabove.
BRIEF DESCRIPTION OF THE DRAWINGS
The foregoing and other features and advantages will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings, in which:
FIG. 1 is a cross-section view schematically and partially illustrating a step of transferring a microchip onto a transfer substrate, according to an example of a method of manufacturing an emissive display device comprising LEDs;
FIG. 2 is a cross-section view schematically and partially illustrating a step of transferring a microchip onto a transfer substrate, according to an embodiment of a method of manufacturing an emissive display device comprising LEDs;
FIG. 3 is a cross-section view schematically and partially illustrating a step of transferring a microchip onto a transfer substrate, according to another embodiment of a method of manufacturing an emissive display device comprising LEDs;
FIG. 4 is a cross-section view schematically and partially illustrating a step of transferring a microchip onto a transfer substrate, according to another embodiment of a method of manufacturing an emissive display device comprising LEDs;
FIGS. 5A, 5B, and 5C are cross-section views illustrating steps of an embodiment of a method of manufacturing an emissive display device comprising LEDs;
FIG. 6 is a cross-section view illustrating an alternative implementation of the method of FIGS. 5A to 5C ;
FIGS. 7A, 7B, 7C, and 7D are cross-section views illustrating steps of another embodiment of a method of manufacturing an emissive display device comprising LEDs;
FIGS. 8A, 8B, 8C, and 8D are cross-section views illustrating steps of another embodiment of a method of manufacturing an emissive display device comprising LEDs;
FIG. 9 is a cross-section view illustrating an alternative implementation of the method of FIGS. 8A to 8D ; and
FIGS. 10A, 10B, 10C, 10D, and 10E are cross-section views illustrating steps of an example of a method of manufacturing a microchip of an emissive display device comprising LEDs according to an embodiment.
DETAILED DESCRIPTION
The same elements have been designated with the same reference numerals in the various drawings and, further, the various drawings are not to scale. For clarity, only those steps and elements which are useful to the understanding of the described embodiments have been shown and are detailed. In particular, the manufacturing of the elementary microchips and of the transfer substrate of the described display devices has not been detailed, the manufacturing of these elements being within the abilities of those skilled in the art based on the teachings of the present description. As an example, the elementary microchips and the transfer substrate may be manufacturing according to methods identical or similar to those described in the above-mentioned French patent application No. 1561421, which is herein incorporated by reference as authorized by law. In the following description, when reference is made to terms qualifying absolute positions, such as terms âfrontâ, ârearâ, âtopâ, âbottomâ, âleftâ, ârightâ, etc., or relative positions, such as terms âaboveâ, âunderâ, âupperâ, âlowerâ, etc., or to terms qualifying directions, such as terms âhorizontalâ, âverticalâ, etc., it is referred to the orientation of the drawings, it being understood that, in practice, the described devices may be oriented differently. The terms âapproximatelyâ, âsubstantiallyâ, and âin the order ofâ are used herein to designate a tolerance of plus or minus 10%, preferably of plus or minus 5%, of the value in question.
FIG. 1 is a cross-section view schematically and partially illustrating a step of transferring a microchip 100 onto a transfer substrate 150 , according to an example of a method of manufacturing an emissive display device comprising LEDs.
FIG. 1 more particularly shows microchip 100 and transfer substrate 150 before the actual step of affixing the microchip onto the transfer substrate.
In particular, a display device may comprise a plurality of identical or similar elementary chips 100 assembled on a same transfer substrate according to a layout in an array of rows and columns, the chips being connected to elements of electric connection of the substrate for the control thereof, and each microchip for example corresponding to a pixel of the display device.
Microchip 100 comprises, in an upper portion, an inorganic semiconductor LED 110 and, in a lower portion forming one piece with the upper portion, an active control circuit 120 based on single-crystal silicon, capable of controlling the emission of light by the LED.
LED 110 comprises at least one homojunction or one heterojunction, for example, a PN junction formed of a stack of an upper N- type semiconductor layer 112 and of a lower P- type semiconductor layer 114 , and two electric contacts 116 and 118 (respectively in contact with layer 112 and with layer 114 in the shown example) to inject an electric current through the stack, in order to generate light. As an example, LED 110 is a gallium nitride LED or is based on any other III-V semiconductor capable of forming a LED.
Control circuit 120 is formed inside and on top of a single- crystal silicon block 121 and comprises electronic components, and particularly one or plurality of transistors and at least one capacitive element for holding a bias signal, for the individual control of LED 110 . The upper surface of control circuit 120 is mechanically and electrically in contact with LED 110 . The lower surface of circuit 120 , defining a connection surface of the microchip, comprises a plurality of electric connection areas intended to be connected to corresponding connection area
This Application is a national stage filing under 35 U.S.C. § 371 of International Patent Application Serial No. PCT/FR2018/051137, filed May 4, 2018, which claims priority to French patent application FR17/54045, filed May 9, 2017, the contents of these applications are incorporated herein by reference in their entirety.
BACKGROUND
The present application concerns the forming of an emissive image display device comprising light-emitting diodes (LEDs), for example, a screen for a television, a computer, a smart phone, a tablet, etc.
DISCUSSION OF THE RELATED ART
A method of manufacturing an image display device comprising a plurality of elementary electronic microchips arranged in an array on a same transfer substrate has already been provided, in French patent application No. 1561421 filed on Nov. 26, 2015. According to this method, the microchips and the transfer substrate are manufactured separately. Each microchip comprises a stack of a LED and of a circuit for controlling the LED. The control circuit comprises a connection surface opposite to the LED, comprising a plurality of electric connection areas intended to be connected to the transfer substrate for the control of the microchip. The transfer substrate comprises a connection surface comprising, for each microchip, a plurality of electric connection areas intended to be respectively connected to the electric connection areas of the microchip. The chips are then placed on the transfer substrate, with their connection surfaces facing the connection surface of the transfer substrate, and affixed to the transfer substrate to connect the electric connection areas of each microchip to the corresponding electric connection areas of the transfer substrate.
It would be desirable to be able to at least partly improve certain aspects of this method.
In particular, due to the relatively small dimensions of the microchips, and given that each microchip comprises a plurality of separate electric connection areas, the alignment of the electric connection areas of the microchips with the corresponding electric connection areas of the transfer substrate is relatively difficult to achieve. It would be desirable to ease the implementation of such an alignment and/or to improve the obtained alignment accuracy.
SUMMARY
Thus, an embodiment provides an electronic device manufacturing method, comprising the steps of:
a) forming a plurality of chips, each comprising:
a plurality of electric connection areas arranged on a connection surface of the chip, and at least one first pad arranged in the vicinity of the chip connection surface;
b) forming a transfer substrate comprising, for each chip:
a plurality of electric connection areas arranged on a connection surface of the transfer substrate, and at least one second pad arranged in the vicinity of the connection surface of the transfer substrate, one of the first and second pads being a permanent magnet and the other one of the first and second pads being either a permanent magnet or made of a ferromagnetic material; and
c) affixing the chips to the transfer substrate by direct bonding to electrically connect the electric connection areas of each chip to the corresponding electric connection areas of the transfer substrate, by using the magnetic force between the first and second pads to align the electric connection areas of the chips with the corresponding electric connection areas of the transfer substrate.
According to an embodiment, in each chip, the first pad emerges on the side of the connection surface of the microchip.
According to an embodiment, in each chip, the first pad is buried under the connection surface of the chip.
According to an embodiment, in each chip, the connection surface of the chip is planar, the electric connection areas of the chip being flush with an external surface of a passivation layer of the chip.
According to an embodiment, the second pads emerge on the side of the connection surface of the transfer substrate.
According to an embodiment, the second pads are buried under the connection surface of the transfer substrate.
According to an embodiment, the connection surface of the transfer substrate is planar, the electric connection areas of the transfer substrate being flush with an external surface of a passivation layer of the transfer substrate.
According to an embodiment, the electric connection areas of the transfer substrate protrude from the connection surface of the transfer substrate.
According to an embodiment:
at the end of step a), the chips are arranged on a support substrate with a pitch between chips smaller than the pitch between chips of the final display device; and
at step c), a plurality of chips are selectively separated from the support substrate at the pitch of the final display device and affixed to the transfer substrate at this same pitch.
According to an embodiment:
at the end of step a), the chips are only laid, with no bonding, on the support substrate; and
at step c), the transfer substrate is brought above the chips, with its connection surface facing the connection surfaces of the chips, to simultaneously collect a plurality of chips at the pitch of the final display device.
According to an embodiment, the support substrate comprises cavities having the chips arranged therein so that the chips are laterally maintained by the cavity walls.
According to an embodiment, the bottom of each cavity of the support substrate is non-planar.
According to an embodiment, each chip comprises a stack of a LED and of an active circuit for controlling the LED.
Another embodiment provides an emissive display device comprising LEDs formed by a method such as defined hereabove.
BRIEF DESCRIPTION OF THE DRAWINGS
The foregoing and other features and advantages will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings, in which:
FIG. 1 is a cross-section view schematically and partially illustrating a step of transferring a microchip onto a transfer substrate, according to an example of a method of manufacturing an emissive display device comprising LEDs;
FIG. 2 is a cross-section view schematically and partially illustrating a step of transferring a microchip onto a transfer substrate, according to an embodiment of a method of manufacturing an emissive display device comprising LEDs;
FIG. 3 is a cross-section view schematically and partially illustrating a step of transferring a microchip onto a transfer substrate, according to another embodiment of a method of manufacturing an emissive display device comprising LEDs;
FIG. 4 is a cross-section view schematically and partially illustrating a step of transferring a microchip onto a transfer substrate, according to another embodiment of a method of manufacturing an emissive display device comprising LEDs;
FIGS. 5A, 5B, and 5C are cross-section views illustrating steps of an embodiment of a method of manufacturing an emissive display device comprising LEDs;
FIG. 6 is a cross-section view illustrating an alternative implementation of the method of FIGS. 5A to 5C ;
FIGS. 7A, 7B, 7C, and 7D are cross-section views illustrating steps of another embodiment of a method of manufacturing an emissive display device comprising LEDs;
FIGS. 8A, 8B, 8C, and 8D are cross-section views illustrating steps of another embodiment of a method of manufacturing an emissive display device comprising LEDs;
FIG. 9 is a cross-section view illustrating an alternative implementation of the method of FIGS. 8A to 8D ; and
FIGS. 10A, 10B, 10C, 10D, and 10E are cross-section views illustrating steps of an example of a method of manufacturing a microchip of an emissive display device comprising LEDs according to an embodiment.
DETAILED DESCRIPTION
The same elements have been designated with the same reference numerals in the various drawings and, further, the various drawings are not to scale. For clarity, only those steps and elements which are useful to the understanding of the described embodiments have been shown and are detailed. In particular, the manufacturing of the elementary microchips and of the transfer substrate of the described display devices has not been detailed, the manufacturing of these elements being within the abilities of those skilled in the art based on the teachings of the present description. As an example, the elementary microchips and the transfer substrate may be manufacturing according to methods identical or similar to those described in the above-mentioned French patent application No. 1561421, which is herein incorporated by reference as authorized by law. In the following description, when reference is made to terms qualifying absolute positions, such as terms âfrontâ, ârearâ, âtopâ, âbottomâ, âleftâ, ârightâ, etc., or relative positions, such as terms âaboveâ, âunderâ, âupperâ, âlowerâ, etc., or to terms qualifying directions, such as terms âhorizontalâ, âverticalâ, etc., it is referred to the orientation of the drawings, it being understood that, in practice, the described devices may be oriented differently. The terms âapproximatelyâ, âsubstantiallyâ, and âin the order ofâ are used herein to designate a tolerance of plus or minus 10%, preferably of plus or minus 5%, of the value in question.
FIG. 1 is a cross-section view schematically and partially illustrating a step of transferring a microchip 100 onto a transfer substrate 150 , according to an example of a method of manufacturing an emissive display device comprising LEDs.
FIG. 1 more particularly shows microchip 100 and transfer substrate 150 before the actual step of affixing the microchip onto the transfer substrate.
In particular, a display device may comprise a plurality of identical or similar elementary chips 100 assembled on a same transfer substrate according to a layout in an array of rows and columns, the chips being connected to elements of electric connection of the substrate for the control thereof, and each microchip for example corresponding to a pixel of the display device.
Microchip 100 comprises, in an upper portion, an inorganic semiconductor LED 110 and, in a lower portion forming one piece with the upper portion, an active control circuit 120 based on single-crystal silicon, capable of controlling the emission of light by the LED.
LED 110 comprises at least one homojunction or one heterojunction, for example, a PN junction formed of a stack of an upper N- type semiconductor layer 112 and of a lower P- type semiconductor layer 114 , and two electric contacts 116 and 118 (respectively in contact with layer 112 and with layer 114 in the shown example) to inject an electric current through the stack, in order to generate light. As an example, LED 110 is a gallium nitride LED or is based on any other III-V semiconductor capable of forming a LED.
Control circuit 120 is formed inside and on top of a single- crystal silicon block 121 and comprises electronic components, and particularly one or plurality of transistors and at least one capacitive element for holding a bias signal, for the individual control of LED 110 . The upper surface of control circuit 120 is mechanically and electrically in contact with LED 110 . The lower surface of circuit 120 , defining a connection surface of the microchip, comprises a plurality of electric connection areas intended to be connected to corresponding connection areas of transfer substrate 150 for the control of the microchip. In the shown example, the lower surface of circuit 120 comprises four
electric connection areas
125 , 126 , 127 , and 128 . Areas
125 and 126 are intended to respectively receive a low power supply potential (for example, the ground) Vn and a high power supply potential (that is, higher than the low power supply potential) Vp of the microchip. Areas
127 and 128 are intended to receive microchip control signals. More particularly, area 127 is intended to receive a microchip selection signal Vsel, and area 128 is intended to receive a signal Vdata for setting the luminosity level of the microchip.
Connection areas
125 , 126 , 127 , and 128 are for example made of metal, for example, of copper, of gold, or of titanium. In the present example, control circuit 120 comprises two MOS transistors
122 and 123 and one capacitive element 124 , for example, a capacitor. Transistor 122 , for example, a P-channel transistor, has a first conduction node (source or drain) connected to the connection area 126 (Vp) of the microchip, a second conduction node (drain or source) connected to the anode contact terminal 118 of LED 110 , and a control node (gate) connected to an intermediate node a 1 of circuit 120 . Capacitive element 124 has a first electrode connected to node a 1 and a second electrode connected to the microchip connection area 126 (Vp). Transistor 123 , for example, an N-channel transistor, has a first conduction node connected to the connection area 128 (Vdata) of the microchip, a second conduction node connected to node a 1 , and a control node connected to the connection area 127 (Vsel) of the microchip. Microchip 100 further comprises an insulated conductive via 129 connecting the electric connection area 125 (Vn) of the microchip to the cathode contact terminal 116 of LED 110 .
Elementary microchip 100 operates as follows during a phase of updating the luminosity level of the pixel. Transistor 123 is turned on (made conductive) by the application of an adapted control signal to terminal 127 (Vsel). Capacitive element 124 then charges to a voltage level which is a function of the adjustment signal applied to terminal 128 (Vdata) of the microchip. The level of adjustment signal Vdata sets the potential of node a 1 and, accordingly, the intensity of the current injected into the LED by transistor 122 , and thus the light intensity emitted by the LED. Transistor 123 can then be turned back off. Node a 1 then remains at a potential substantially equal to potential Vdata. Thus, the current injected into the LED remains substantially constant after the turning back off of transistor 123 , and this, until the next update of the potential of node a 1 .
Transfer substrate 150 for example comprises a support plate or sheet 151 made of an insulating material, having electric connection elements, for example, conductive tracks and areas, arranged thereon. Transfer substrate 150 is for example a passive substrate, that is, it only comprises electric connection elements for conveying the microchip control and power supply signals. Transfer substrate 150 comprises a connection surface, its upper surface in the shown example, intended to receive microchips 100 . For each microchip of the display device, transfer substrate 150 comprises, on its connection surface, a plurality of electric connection areas (one per electric connection area of the microchip) intended to be respectively connected to the electric connection areas of the microchip. Thus, in the present example, for each microchip 100 of the display device, transfer substrate 150 comprises four
electric connection areas
155 , 156 , 157 , and 158 intended to be respectively connected to electric connection areas
125 , 126 127 , and 128 of microchip 100 , to convey control signals Vn, Vp, Vsel, and Vdata of the microchip. The
electric connection areas
155 , 156 , 157 , and 158 of the transfer substrate are for example made of the same conductive material as the
electric connection areas
125 , 126 , 127 , and 128 of the microchips, for example, copper, gold, or titanium.
During the transfer of microchip 100 onto transfer substrate 150 , the connection surface of the microchip is placed in contact with the connection surface of the transfer substrate to electrically connect the
electric connection areas
125 , 126 , 127 , and 128 of the microchip respectively to the corresponding
electric connection areas
155 , 156 , 157 , and 158 of the transfer substrate. The affixing of microchip 100 to the transfer substrate is performed by direct bonding, that is, with no added adhesive or solder material at the interface between the microchip and the substrate, for example, at ambient temperature and pressure. To achieve this, the electric connection areas of the microchip and of the transfer substrate may have been previously prepared to obtain a sufficient planeness, for example, a roughness lower than 1 nm, to achieve a direct bonding of areas 125 , respectively 126 , respectively 127 , respectively 128 , on areas 155 , respectively 156 , respectively 157 , respectively 158 . An anneal may possibly be provided after the bonding, for example, at a temperature in the range from 150 to 250° C., to increase the strength of the bonding.
As indicated hereabove, a difficulty of such a method is the alignment of the electric connection areas of the microchip with the corresponding electric connection areas of the transfer substrate to obtain a good electric connection between the microchip and the transfer substrate.
Indeed, the microchips for example have, in top view, a maximum dimensions smaller than or equal to 100 μm, for example, smaller than or equal to 50 μm, for example, in the order of 10 μm. Each microchip comprising a plurality of electric connection areas (four in the example of FIG. 1 ), the microchip alignment should be very accurate, for example, with an accuracy better than to within 1 μm.
FIG. 2 is a cross-section view schematically and partially illustrating a step of transferring a microchip 200 onto a transfer substrate 250 , according to an embodiment of a method of manufacturing an emissive display device comprising LEDs. FIG. 2 more particularly shows microchip 200 and transfer substrate 250 before the actual step of affixing the microchip onto the transfer substrate.
Microchip 200 and transfer substrate 250 of FIG. 2 comprise elements common with microchip 100 and transfer substrate 150 of FIG. 1 . Hereafter, only the differences between the embodiment of FIG. 2 and the example of FIG. 1 will be detailed.
Microchip 200 of FIG. 2 comprises the same elements as microchip 100 of FIG. 1 , arranged substantially in the same way, and differs from microchip 100 of FIG. 1 mainly in that it further comprises, in the vicinity of its connection surface, that is, closer to its connection surface than to its opposite surface, a pad 202 made of a ferromagnetic material, for example, of a nickel-iron alloy.
In the example of FIG. 2 , pad 202 emerges on the side of the connection surface of the microchip.
Further, in the present example, the connection surface of microchip 200 is substantially planar, that is, the
electric connection areas
125 , 126 , 127 , and 128 and the ferromagnetic pad 202 of the microchip are flush with the lower surface of a substantially planar insulating layer 203 for passivating the microchip. As an example, the
electric connection areas
125 , 126 , 127 , and 128 and the ferromagnetic pad 202 of the microchip are formed according to a damascene-type method, comprising a step of depositing insulating passivation layer 203 over the entire lower surface of the microchip, followed by a step of etching cavities intended to receive
electric connection areas
125 , 126 , 127 , and 128 and pad 202 on the lower surface side of the microchip, followed by a step of filling the cavities with a conductive material to form the electric connection areas and with a ferromagnetic material to form pad 202 , followed by a step of chem.-mech. polishing to planarize the lower surface of the chip to place at a same level the lower surfaces of
electric connection areas
125 , 126 , 127 , and 128 and of pad 202 , and the lower surface of passivation layer 203 .
As an example, the
electric connection areas
125 , 126 , 127 , and 128 of microchip 200 are made of the same material as ferromagnetic pad 202 , which simplifies the microchip manufacturing method.
The transfer substrate 250 of FIG. 2 comprises the same elements as the transfer substrate 150 of FIG. 1 and differs from the transfer substrate 150 of FIG. 1 mainly in that it further comprises, in the vicinity of its connection surface, that is, closer to its connection surface than to its opposite surface, for each microchip 200 of the display device, in addition to the
connection areas
155 , 156 , 157 , and 158 intended to be connected to the
connection areas
125 , 126 , 127 , and 128 of the microchip, a permanent magnet 252 forming a pad having, in front view, substantially the same general shape and the same dimensions as the ferromagnetic pad 202 of the microchip.
The positioning of pad 252 relative to the
electric connection areas
155 , 156 , 157 and 158 of the transfer substrate is substantially identical to the positioning of pad 202 relative to the
electric connection areas
125 , 126 , 127 , and 128 of the microchip. In other words, when the
electric connection areas
125 , 126 , 127 , and 128 of the microchip are aligned respectively vertically in line with the
electric connection areas
155 , 156 , 157 , and 158 of the transfer substrate, the ferromagnetic pad 202 of the microchip is located vertically in line with the permanent magnet 252 of the transfer substrate.
In the example of FIG. 2 , magnet pad 252 emerges on the side of the connection area of the transfer substrate.
Further, in the present example, the connection surface of the transfer substrate is substantially planar, that is, the
electric connection areas
155 , 156 , 157 , and 158 and the magnet pad 252 of the transfer substrate are flush with the level of the upper surface of a substantially insulating layer 253 for passivating the transfer substrate. As an example, the
electric connection areas
155 , 156 , 157 , and 158 and the magnet pad 252 of the transfer substrate are formed according to a damascene-type method, comprising a step of depositing insulating passivation layer 253 over the entire upper surface of the transfer substrate, followed by a step of etching cavities intended to receive
electric connection areas
155 , 156 , 157 , and 158 and pad 252 on the upper surface side of the transfer substrate, followed by a step of filling the cavities with a conductive material to form the electric connection areas and with a permanent magnet material to form pad 252 , followed by a step of chem.-mech. polishing to planarize the upper surface of the substrate to place at a same level the upper surfaces of
electric connection areas
155 , 156 , 157 , and 158 and of pad 252 , and the upper surface of passivation layer 253 .
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CLAIMS
Claims ( 14 )
The invention claimed is:
1. A method of manufacturing an electronic device, comprising the steps of:
a) forming a plurality of chips, each comprising:
at least one LED;
an active circuit for controlling the at least one LED,
on a lower surface of the active circuit of the chip, a first, a second, a third, and a fourth electric connection areas, the first, second, third, and fourth electric connection areas being intended to receive respectively a low power supply potential, a high power supply potential, a chip selection signal, and a luminosity data signal, the first electric connection area being connected to a terminal of the at least one LED by a conductive via extending vertically through the active circuit; and
at least one first pad arranged in the vicinity of the lower surface of the active circuit of the chip;
b) forming a transfer substrate separate from the plurality of chips, the transfer substrate comprising, for each chip:
on an upper surface of the transfer substrate, a first, a second, a third, and a fourth electric connection area intended to be respectively connected to the first, second, third, and fourth electric connection areas of the active circuit of the chip; and
at least one second pad arranged in the vicinity of the upper surface of the transfer substrate, one of the first and second pads being a permanent magnet and the other of the first and second pads being either a permanent magnet or made of a ferromagnetic material; and
c) affixing the chips to the transfer substrate by direct bonding to electrically connect the electric connection areas of each chip to the corresponding electric connection areas of the transfer substrate, by using the magnetic force between the first and second pads to align the electric connection areas of the chips with the corresponding electric connection areas of the transfer substrate,
wherein affixing the chips to the transfer substrate includes electrically connecting the at least one LED and the active circuit of each chip to the corresponding electric connection areas of the transfer substrate;
wherein the active circuit of each chip comprises:
a first metal-oxide-semiconductor (MOS) transistor having a first conduction node connected to the second electric connection area and a second conduction node connected to a second terminal of the at least one LED;
a second MOS transistor having a first conduction node connected to a gate of the first MOS transistor, a second conduction node connected to the fourth electric connection area, and a gate connected to the third electric connection area; and
at least one capacitive element for holding a bias signal for the individual control of the at least one LED.
2. The method of claim 1 , wherein, in each chip, the first pad emerges on the side of the connection surface of the microchip.
3. The method of claim 1 , wherein, in each chip the first pad is buried under the connection surface of the chip.
4. The method of claim 1 , wherein, in each chip, the connection surface of the chip is planar, the electric connection areas of the chip being flush with an external surface of a passivation layer of the chip.
5. The method of claim 1 , wherein the second pads emerge on the side of the connection surface of the transfer substrate.
6. The method of claim 1 , wherein the second pads are buried under the connection surface of the transfer substrate.
7. The method of claim 1 , wherein, in each chip, the connection surface of the transfer substrate is planar, the electric connection areas of the transfer substrate being flush with an external surface of a passivation layer of the transfer substrate.
8. The method of claim 1 , wherein the electric connection areas of the transfer substrate protrude from the connection surface of the transfer substrate.
9. The method of claim 1 , wherein:
at the end of step a), the chips are arranged on a support substrate with a pitch between chips smaller than the pitch between chips of the final display device; and
at step c), a plurality of chips are selectively separated from the support substrate at the pitch of the final display device and affixed to the transfer substrate at this same pitch.
10. The method of claim 9 , wherein:
at the end of step a), the chips are only laid, with no bonding, on the support substrate; and
at step c), the transfer substrate is brought above the chips, with its connection surface facing the connection surfaces of the chips, to simultaneously collect a plurality of chips at the pitch of the final display device.
11. The method of claim 10 , wherein the support substrate comprises cavities having the chips arranged therein so that the chips are laterally held by the cavity walls.
12. The method of claim 11 , wherein the bottom of each cavity of the support substrate is non-planar.
13. An emissive display device comprising LEDs formed by the method of claim 1 .
14. The method of claim 1 , wherein at step c), the direct bonding is performed at ambient temperature and pressure.
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