RevaMp3D: Architecting the Processor Core and Cache Hierarchy for Systems with Monolithically-Integrated Logic and Memory

[2210.08508] RevaMp3D: Architecting the Processor Core and Cache Hierarchy for Systems with Monolithically-Integrated Logic and Memory Skip to main content Search Submit Donate Log in Search arXiv Press Enter to search · Advanced search Computer Science > Hardware Architecture arXiv:2210.08508 (cs) [Submitted on 16 Oct 2022 ( v1 ), last revised 15 Aug 2026 (this version, v4)] Title: RevaMp3D: Architecting the Processor Core and Cache Hierarchy for Systems with Monolithically-Integrated Logic and Memory Authors: Nika Mansouri Ghiasi , Mohammad Sadrosadati , Geraldo F. Oliveira , Konstantinos Kanellopoulos , Rachata Ausavarungnirun , Juan Gómez Luna , João Ferreira , Jeremie S. Kim , Christina Giannoula , Nandita Vijaykumar , Jisung Park , Onur Mutlu View a PDF of the paper titled RevaMp3D: Architecting the Processor Core and Cache Hierarchy for Systems with Monolithically-Integrated Logic and Memory, by Nika Mansouri Ghiasi and 11 other authors View PDF HTML (experimental) Abstract: Recent nano-technological advances enable the Monolithic 3D (M3D) integration of multiple memory and logic layers in a single chip, allowing for fine-grained connections between layers and significantly alleviating main memory bottlenecks. We show for a variety of workloads, on a state-of-the-art M3D-based system, that the performance and energy bottlenecks shift from main memory to the processor core and cache hierarchy. Therefore, there is a need to revisit current designs that have been conventionally tailored to tackle the memory bottleneck. Based on the insights from our design space exploration, we propose RevaMp3D, introducing five key changes. First, we propose removing the shared last-level cache, as this delivers speedups comparable to or exceeding those from increasing its size or reducing its latency across all workloads. Second, since improving L1 cache latency has a large impact on performance, we reduce L1 latency by leveraging an M3D layout to shorten its wires. Third, we repurpose the area from the removed cache to widen and scale up pipeline structures, accommodating more in-flight requests that are efficiently served by M3D memory. To avoid latency penalties from these larger structures, we leverage M3D layouts. Fourth, to facilitate high thread-level parallelism, we propose a new fine-grained synchronization technique, using M3D's dense inter-layer connectivity. Fifth, we leverage the M3D main memory to mitigate the core bottlenecks. We propose a processor frontend design that memoizes the repetitive fetched, decoded, and reordered instructions, stores them in main memory, and turns off the relevant parts of the core when possible. RevaMp3D provides 1.2x-2.9x speedup and 1.2x-1.4x energy reduction compared to a state-of-the-art M3D system. We also analyze RevaMp3D's design decisions across various memory latencies to facilitate latency-aware design decisions. Comments: Extended version of the paper published in TACO 2026 Subjects: Hardware Architecture (cs.AR) ; Distributed, Parallel, and Cluster Computing (cs.DC) Cite as: arXiv:2210.08508 [cs.AR] (or arXiv:2210.08508v4 [cs.AR] for this version) https://doi.org/10.48550/arXiv.2210.08508 Focus to learn more arXiv-issued DOI via DataCite Submission history From: Nika Mansouri Ghiasi [ view email ] [v1] Sun, 16 Oct 2022 11:21:26 UTC (402 KB) [v2] Sun, 8 Jun 2025 16:07:44 UTC (472 KB) [v3] Thu, 22 Jan 2026 23:08:40 UTC (525 KB) [v4] Sat, 15 Aug 2026 10:16:17 UTC (556 KB) Full-text links: Access Paper: View a PDF of the paper titled RevaMp3D: Architecting the Processor Core and Cache Hierarchy for Systems with Monolithically-Integrated Logic and Memory, by Nika Mansouri Ghiasi and 11 other authors View PDF HTML (experimental) TeX Source view license Current browse context: cs.AR < prev | next > new | recent | 2022-10 Change to browse by: cs cs.DC References & Citations NASA ADS Google Scholar Semantic Scholar export BibTeX citation Loading... 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