WWW: What, When, Where to Compute-in-Memory
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[2312.15896] WWW: What, When, Where to Compute-in-Memory Skip to main content Search Submit Donate Log in Search arXiv Press Enter to search · Advanced search Computer Science > Hardware Architecture arXiv:2312.15896 (cs) [Submitted on 26 Dec 2023 ( v1 ), last revised 27 Feb 2025 (this version, v3)] Title: WWW: What, When, Where to Compute-in-Memory Authors: Tanvi Sharma , Mustafa Ali , Indranil Chakraborty , Kaushik Roy View a PDF of the paper titled WWW: What, When, Where to Compute-in-Memory, by Tanvi Sharma and 3 other authors View PDF HTML (experimental) Abstract: Matrix multiplication is the dominant computation during Machine Learning (ML) inference. To efficiently perform such multiplication operations, Compute-in-memory (CiM) paradigms have emerged as a highly energy efficient solution. However, integrating compute in memory poses key questions, such as 1) What type of CiM to use: Given a multitude of CiM design characteristics, determining their suitability from architecture perspective is needed. 2) When to use CiM: ML inference includes workloads with a variety of memory and compute requirements, making it difficult to identify when CiM is more beneficial than standard processing cores. 3) Where to integrate CiM: Each memory level has different bandwidth and capacity, creating different data reuse opportunities for CiM integration. To answer such questions regarding on-chip CiM integration for accelerating ML workloads, we use an analytical architecture-evaluation methodology with tailored mapping algorithm. The mapping algorithm aims to achieve highest weight reuse and reduced data movements for a given CiM prototype and workload. Our analysis considers the integration of CiM prototypes into the cache levels of a tensor-core-like architecture, and shows that CiM integrated memory improves energy efficiency by up to 3.4x and throughput by up to 15.6x compared to established baseline with INT-8 precision. We believe the proposed work provides insights into what type of CiM to use, and when and where to optimally integrate it in the cache hierarchy for efficient matrix multiplication. Comments: added supplementary Subjects: Hardware Architecture (cs.AR) ; Distributed, Parallel, and Cluster Computing (cs.DC); Machine Learning (cs.LG) Cite as: arXiv:2312.15896 [cs.AR] (or arXiv:2312.15896v3 [cs.AR] for this version) https://doi.org/10.48550/arXiv.2312.15896 Focus to learn more arXiv-issued DOI via DataCite Journal reference: IEEE Transactions on Emerging Topics in Computing 2025.03 Related DOI : https://doi.org/10.1109/TETC.2025.3574508 Focus to learn more DOI(s) linking to related resources Submission history From: Tanvi Sharma [ view email ] [v1] Tue, 26 Dec 2023 06:16:12 UTC (4,019 KB) [v2] Thu, 20 Jun 2024 14:29:16 UTC (3,733 KB) [v3] Thu, 27 Feb 2025 21:50:48 UTC (8,010 KB) Full-text links: Access Paper: View a PDF of the paper titled WWW: What, When, Where to Compute-in-Memory, by Tanvi Sharma and 3 other authors View PDF HTML (experimental) TeX Source view license Current browse context: cs.AR < prev | next > new | recent | 2023-12 Change to browse by: cs cs.DC cs.LG References & Citations NASA ADS Google Scholar Semantic Scholar export BibTeX citation Loading... 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