Characterization of a 28 nm $\textit{smartpixels}$ ASIC With On-Chip ML for Particle Tracking Detectors

[2510.07485] Characterization of a 28 nm $\textit{smartpixels}$ ASIC With On-Chip ML for Particle Tracking Detectors Skip to main content Search Submit Donate Log in Search arXiv Press Enter to search · Advanced search Physics > Instrumentation and Detectors arXiv:2510.07485 (physics) [Submitted on 8 Oct 2025 ( v1 ), last revised 15 Aug 2026 (this version, v3)] Title: Characterization of a 28 nm $\textit{smartpixels}$ ASIC With On-Chip ML for Particle Tracking Detectors Authors: Benjamin Parpillon , Anthony Badea , Danush Shekar , Cristian Gingu , Giuseppe Di Guglielmo , Tom Deline , Sergey Los , Adam Quinn , Michele Ronchi , Daniel Abadjiev , Doug Berry , Arghya Ranjan Das , Jennet Dickinson , Karri DiPetrillo , Farah Fahim , Lindsey Gray , Harshul Gupta , Eliza Howard , David Jiang , Pamela Klabbers , Mira Littmann , Mia Liu , Petar Maksimovic , Nick Manganelli , Corrinne Mills , Mark S. Neubauer , Jannicke Pearkes , Paul Rubinov , Ricardo Silvestre , Morris Swartz , Chinar Syal , Nhan Tran , Amit Trivedi , Keith Ulmer , Mohammad Abrar Wadud , Benjamin Weiss , Jieun Yoo , Eric You View a PDF of the paper titled Characterization of a 28 nm $\textit{smartpixels}$ ASIC With On-Chip ML for Particle Tracking Detectors, by Benjamin Parpillon and 37 other authors View PDF HTML (experimental) Abstract: We present a 28 nm CMOS pixel readout integrated circuit implementing in-pixel analog signal processing and on-chip machine learning data filtering for particle tracking detectors. Our ASIC comprises two $32 \times 8$ pixel matrices with a pixel pitch of $25 \times 25~\mu\mathrm{m}^2$, in which each pixel integrates a charge-sensitive amplifier with synchronous auto-zero offset cancellation and a 2-bit flash ADC with programmable thresholds. Two analog front-end architectures, single-ended and differential, are implemented and characterized. Digitized pixel data are combined into row-wise projections and processed by an on-chip, fully combinational neural network classifier for data reduction. Measurements at room temperature using charge injection demonstrate an equivalent noise charge of $54.6~\mathrm{e}^{-}$ and a threshold dispersion of $\sim$78.2~\unit{\electron} at nominal bias, linear response up to several~\unit{\kilo\electron}, and stable operation at a 10~MHz clock frequency. The neural network output is compared with offline RTL predictions and agrees for $99.06\%$ of $1.5 \times 10^{5}$ test inputs. Subjects: Instrumentation and Detectors (physics.ins-det) ; High Energy Physics - Experiment (hep-ex); Nuclear Experiment (nucl-ex) Cite as: arXiv:2510.07485 [physics.ins-det] (or arXiv:2510.07485v3 [physics.ins-det] for this version) https://doi.org/10.48550/arXiv.2510.07485 Focus to learn more arXiv-issued DOI via DataCite Submission history From: Danush Shekar [ view email ] [v1] Wed, 8 Oct 2025 19:35:15 UTC (29,651 KB) [v2] Tue, 14 Oct 2025 16:08:40 UTC (29,651 KB) [v3] Sat, 15 Aug 2026 02:06:14 UTC (28,581 KB) Full-text links: Access Paper: View a PDF of the paper titled Characterization of a 28 nm $\textit{smartpixels}$ ASIC With On-Chip ML for Particle Tracking Detectors, by Benjamin Parpillon and 37 other authors View PDF HTML (experimental) TeX Source view license Current browse context: physics.ins-det < prev | next > new | recent | 2025-10 Change to browse by: hep-ex nucl-ex physics References & Citations INSPIRE HEP NASA ADS Google Scholar Semantic Scholar export BibTeX citation Loading... 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