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Exploiting Per-Core Leakage: Electromagnetic Side-Channel Monitoring of Multicore Architectures

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arXiv:2608.28412v1 [cs.CR] 28 Aug 2026

Exploiting Per-Core Leakage: Electromagnetic Side-Channel Monitoring of Multicore Architectures Daehyeon Bae

Sujin Park

Insup Lee

Younggiu Jung

Korea University Seoul, South Korea dh_bae@korea.ac.kr

Korea University Seoul, South Korea lemontrees33@korea.ac.kr

Korea University Seoul, South Korea islee94@korea.ac.kr

YM-NaeulTech. Incheon, South Korea youngq.jung@ym-naeultech.com

Kyeongsik Lee

HeeSeok Kim∗

Seokhie Hong

Agency for Defense Development Seoul, South Korea n0fate@add.re.kr

Korea University Sejong, South Korea 80khs@korea.ac.kr

SmartM2M Busan, South Korea shhong@smartm2m.co.kr

Abstract Multicore processors are increasingly adopted in embedded systems to meet growing performance demands. However, physical side-channel analysis of multicore architectures remains underexplored, as obtaining usable leakage is inherently challenging. Consequently, side-channel security research on such systems has lagged far behind, leaving a critical security gap. To address this gap, we reveal the electromagnetic leakage mechanisms in multicore architectures and, for the first time, demonstrate per-core leakage exploitation, thereby enabling physical side-channel analysis for these systems. As a practical extension, we present a non-intrusive side-channel monitoring method that achieves per-core granularity. To validate its feasibility and practicality, we implement a prototype on a heterogeneous SoC platform with an RF front-end, and evaluate on a commercial off-the-shelf quad-core embedded system, the Raspberry Pi 4B with ARM Cortex-A72 cores.

Keywords Hardware security, Side-channel analysis, Multicore architecture ACM Reference Format: Daehyeon Bae, Sujin Park, Insup Lee, Younggiu Jung, Kyeongsik Lee, HeeSeok Kim, and Seokhie Hong. 2026. Exploiting Per-Core Leakage: Electromagnetic Side-Channel Monitoring of Multicore Architectures. In 63rd ACM/IEEE Design Automation Conference (DAC ’26), July 26–29, 2026, Long Beach, CA, USA. ACM, New York, NY, USA, 7 pages. https://doi.org/10.1145/3770743.3803928

Introduction

Advances in computing architectures have made physical sidechannel analysis increasingly difficult. In particular, multicore architectures remain largely unexplored, as no effective solution has been proposed to address challenges arising from inter-core signal interference, signal heterogeneity, and dynamic core assignment driven by CPU scheduling policies and core affinity configurations. Consequently, the field has fallen behind not only in cryptographic security evaluation but also in side-channel monitoring. ∗ Corresponding author. This work was supported by the Agency for Defense

Development by the Korean government (No. UG243060TD).

This work is licensed under a Creative Commons Attribution 4.0 International License. DAC ’26, Long Beach, CA, USA © 2026 Copyright held by the owner/author(s). ACM ISBN 979-8-4007-2254-7/2026/07 https://doi.org/10.1145/3770743.3803928

Side-channel monitoring has recently gained significant attention as a promising security approach for observing power or electromagnetic (EM) signals externally from embedded systems, where on-device security solutions are inherently difficult to deploy [11, 20]. Although multicore architectures are increasingly adopted in embedded systems to meet higher performance demands, research on such platforms remains limited, leaving a critical security gap. While some argue that multicore systems can seemingly host security solutions, side-channel monitoring in these systems remains both necessary and beneficial for the following reasons: ✽ Persistent Resource Constraints. While increasing the number of cores generally enhances performance, overall system capability is also determined by the underlying microarchitecture of individual cores, memory and storage capacity, and I/O bandwidth. In fact, security solutions such as IDS, IPS, and antivirus software are resource-intensive—particularly in terms of memory and storage, often exceeding CPU requirements—making them difficult to deploy on multicore embedded systems. ✽ Zero-Overhead. The overhead introduced by on-device security solutions can undermine the consistency of latency and throughput, which is often unacceptable in mission-critical systems— especially in military and aerospace contexts [9]. Side-channel monitoring, however, avoids such overhead entirely, as it does not rely on the target device’s hardware resources. ✽ Stealth Monitoring. Some sophisticated malware actively probes the system for signs of security components and initiates evasion strategies upon their discovery [3, 17]. Side-channel monitoring, however, operates in a completely separate domain, making its execution entirely invisible to the target system. Previous Approaches and Limitations. Only a few studies have explicitly addressed physical side channels in multicore systems [29, 30, 39], excluding microarchitectural or cache-level work beyond the scope of this study [18, 25, 26, 31]. Yilmaz et al. first explored side-channel monitoring on multicore systems, and their study remains the sole work in this domain [39]. Their approach, however, relies on aggregated EM leakage—observed without considering the leakage mechanisms in multicore architectures—thereby leading to high complexity and unrealistic assumptions. Navanesan et al. investigated forensics using coarse-grained EM leakage in multicore systems, but their study was limited to cores under different clock domains [30]. Masti et al. addressed inter-core thermal covert channels, which are not directly relevant to our work [29].

Daehyeon Bae, Sujin Park, Insup Lee, Younggiu Jung, Kyeongsik Lee, HeeSeok Kim, and Seokhie Hong

Organization. The remainder of this paper is organized as follows: Section 2 analyzes the EM leakage mechanisms in multicore architectures and analyzes the meaning of their spectral patterns. Section 3 proposes a detailed method that enables side-channel monitoring on multicore architectures. Section 4 presents the prototype implementation and experimental results. Section 5 discusses the limitations, and Section 6 concludes the paper.

EM Leakage in Multicore Architectures

We begin with a review of prior work on single-core EM leakage (§2.1), followed by our own analysis and findings (§2.2–§2.3), and finally extend the analysis to multicore architectures (§2.4).

2.1

Prior Work — Single-Core Leakage

Previous studies have shown that EM side-channel leakage mainly arises from amplitude modulation [4, 10]. This modulation produces sideband patterns that are highly dependent on CPU core activity and have been widely exploited in the literature [15, 34, 35]. These sidebands are known to reflect periodic activity in the CPU core, with spectral peaks appearing at 𝑓c ± 𝑛· 1/𝑇 , where 𝑓c denotes the clock frequency and 𝑇 is the period of the repeated activity, and 𝑛 ∈ N. However, the mechanism behind sideband generation and its precise relationship with CPU activity remain not fully understood.

2.2

Sideband Formation and Interpretation

How Sidebands Are Formed. A significant portion of EM sidechannel leakage from CPU core originates in the on-chip power delivery network [8, 24]. At each rising edge of the clock signal, CMOS circuits—comprising the CPU core—draw current as a result of switching activity, generating EM emissions at the clock

Baseband

30 20 10 0 100 150 200 800

RF Band (Carrier Freq.) Mag. (1e-3)

15 10 5 0

900

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1,200

1,000

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950 1,000 1,050 Frequency [MHz]

1,100

(a) Type-2 sideband

2 1 0

20 40 60 80 100

4 2 0 900

Mag. (1e-3)

Our Approach and Contributions. To achieve practical and lowcomplexity side-channel monitoring, we pursue an approach that leverages usable per-core leakage. In this context, we employ a finegrained multi-probing that directly measures non-aggregated EM leakage at individual cores. While multi-probing has been shown to capture the leakage of individual circuits in FPGA-based cryptographic implementations [7, 36], extending this technique to multicore processors remains highly challenging due to the difficulty of identifying per-core leakage sources, inter-core interference, signal heterogeneity, and dynamic core assignment. In this work, building on our analysis of EM leakage mechanisms in multicore architectures, we address these inherent challenges and present the first method achieving per-core leakage exploitation. We summarize our contributions as follows: ✽ We reveal the EM leakage mechanisms in multicore architectures and, for the first time, demonstrate per-core leakage exploitation, thereby enabling physical side-channel analysis for these systems. ✽ We analyze processor EM leakage spectra to characterize their patterns and implications, and based on these findings, propose an autoencoder-based side-channel monitoring method designed to be core-agnostic. ✽ To demonstrate feasibility and practicality, we implement a prototype device based on a heterogeneous SoC platform. We further validate it on a commercial off-the-shelf quad-core system, Raspberry Pi 4B with ARM Cortex-A72 cores.

950

(b) Type-3 sideband

1.5 1 0.5 0

20 40 60 80 100 Frequency [MHz]

3 2 1 0 900

Mag. (1e-3)

DAC ’26, July 26–29, 2026, Long Beach, CA, USA

Figure 1: Atomic sideband patterns by activity type. These patterns were derived from AM simulations using a non-sinusoidal carrier and an arbitrary modulator to mimic EM leakage from CPU activity.

frequency near the on-chip power rail. These emissions act as a carrier whose waveform depends on current draw. When different instructions are executed in the CPU core, distinct circuit blocks become active, leading to changes in current on the power rail that modulate the carrier signal. This serves as an amplitude modulator, leading to the formation of distinct sidebands. This claim is supported by the equivalence between the sideband patterns measured at the decoupling capacitors—connected to the CPU core’s power rail—and those observed at the silicon die. What Sidebands Reveal. As established earlier, sidebands are fundamentally linked to the current drawn from the CPU core’s power rail. In this sense, the core’s power consumption is indirectly encoded in the sidebands. Then, how exactly are the sideband patterns related to power consumption? As demonstrated by the simulations in §2.3, the non-sinusoidal nature of the carrier and the arbitrary modulating signal (power consumption) result in sideband patterns that are identical to the Fourier transform of the baseband signal— simply shifted and scaled by the carrier or its harmonics. Thus, the sideband pattern corresponds to a frequency-shifted Fourier representation of the CPU core’s power consumption.

2.3

Spectral Patterns

In this subsection, we present atomic sideband patterns that can emerge in EM leakage based on simulation results. The simulation models a non-sinusoidal carrier that is amplitude-modulated with a baseband signal mimicking CPU power consumption. Type-1— Idle State. Some processors enter low-power modes by applying clock or power gating techniques when CPU operations are unnecessary, aiming to improve power efficiency. In such states, the core becomes inactive, suppressing amplitude modulation and thereby preventing sideband formation. Consequently, the resulting spectrum is clean, exhibiting either a single peak at the carrier frequency or no detectable carrier at all. Type-2— Strictly-Periodic Activity. Repetitive activities are common in embedded systems due to their inherent nature [35]. When such repetition occurs in strictly identical cycles, the sideband pattern appears in the form of 𝑓c ± 𝑛·1/𝑇 , as introduced in §2.1, with

Voltage Regulator (DC-DC Converter)

Power Source (𝑉𝐷𝐷 )

Power Delivery Network

Exploiting Per-Core Leakage: Electromagnetic Side-Channel Monitoring of Multicore Architectures

Power Domain 1

GPU

GPU Power Rail

Power Domain N

Core0 Logic Core1 Logic

Power Domain 3

Core2 Logic

PMIC PMIC (External Power)

Core3 Power Rail

Decoupling Capacitors

Aggregated EM Leakage

(for stabilizing 𝑉𝑐𝑜𝑟𝑒 )

Core0

Virtual Power Rail

Localized Per-Core EM Leakage

Power Domain 2

Core1

Core2

Core3

Virtual Power Rail

Core3 Logic

BCM2711

Core0

Virtual Power Rail

Figure 2: Core-level EM leakage in a multicore processor. EM leakage is observed to be dominant and spatially localized near the virtual power rails of individual cores formed on the VDD plane. The corresponding on-chip power rails are indirectly identified through surface scanning with a horizontal coil (refer to §3.2).

energy concentrated at a few sharp peaks—making them significantly higher than those of other types, as shown in Figure 1(a). Type-3— Jittered-Periodic Activity. Repetitive behavior commonly exhibits slight jitter, especially when loops contain conditional branches. This case represents a variant of Type-2, where sharp peaks are spread into bumps. The center frequencies of the bumps are slightly shifted in proportion to the accumulated jitter, as shown in Figure 1(b). Type-4— Irregular Activity. Most software includes execution segments that appear (pseudo-) random and non-repetitive. In such cases, unlike Type-2 and Type-3, the sideband does not exhibit peaks or bumps but instead forms a broad lobe centered around the carrier frequency, as shown in Figure 1(c). Due to their similar appearance, such patterns tend to lack distinct features, which makes them more difficult to model compared to other types. For these reasons, this type remains largely unaddressed in the literature. Compositional Space of Spectral Patterns. All EM side-channel spectra manifest as superpositions (or instances) of selected patterns from Type-1 to Type-4, resulting from their concatenation in the time domain. Such concatenation inherently causes spectral leakage and slight deformation of the pattern, which are mitigated when a single pattern occupies a larger portion of the transform window.

2.4

Extending to Multicore Architectures

Conceptually, multicore architectures consist of multiple cores fabricated on the same silicon die, each executing instruction-specific circuitry in the same manner. At the die level, each core draws current from its own on-chip power rail, resulting in localized EM leakage near the respective rail, as shown in Figure 2. However, no prior work has demonstrated a way to isolate such localized leakages without inter-core interference. Consequently, only complex, superposed signals have been observed, hindering further progress in this area. If each leakage source could be spatially identified and inter-core interference mitigated, the single-core-level leakage characteristics could naturally extend to the multicore context, which is what this work enables.

DAC ’26, July 26–29, 2026, Long Beach, CA, USA

Proposed Method

A high-level overview of the proposed method is provided in Figure 3. The specific workflow slightly differs depending on whether the modeling or monitoring phase is being conducted. The overall procedure consists of two primary phases as follows: ✽ Modeling phase : 1 → 2 → 3 → 4 → × ✽ Monitoring phase : × → 2 → 3 → × → 5

3.1

Threat Model

We assume a scenario similar to conventional profiled side-channel analysis [13, 38], where normal behavior is modeled on a profiling device and the resulting model is subsequently used to monitor multiple target devices. The profiling device must be capable of executing the target software under the same conditions as the target devices, but it requires no knowledge of the software itself. The only privilege required on the profiling device is the ability to run small instruction sequences—gadgets—with core affinity. Our target devices are embedded systems designed for missionspecific tasks, excluding general-purpose platforms such as smartphones, tablets, and laptops. For example, our approach is wellsuited for detecting abnormal behavior during inspection stages of military command and weapon systems, including communication platforms, missile systems, and unmanned aerial vehicles (UAVs). Since we assume a fixed clock frequency, we do not consider dynamic voltage and frequency scaling (DVFS) in this work.

3.2

Decoupled Per-Core Probing (DPP)

In general, leakage sources on a chip are identified through leakage localization, which yields a leakage map [8, 14, 22, 23]. However, the leakage map on the chip surface is not invariant; it varies depending on probing factors—such as coil orientation, diameter, angle, and height—which also alter inter-core interference characteristics. Accordingly, the key idea is to acquire leakage maps under diverse configurations and to identify, for each core, the probing location and conditions that minimize interference from neighboring cores. To this end, multiple leakage maps are first acquired, from which a Core Selection Map (M𝑐𝑠 ) is derived using Algorithm 1. The most straightforward and effective way to obtain diverse leakage maps is to vary the rotation angle of the coil with respect to the chip’s origin. For the acquisition of leakage maps, we employ an instruction snippet—referred to as a gadget (e.g., see Figure 4)—which is designed to generate an artificial Type-2 sideband leakage. Since the sideband peaks directly reflect the underlying leakage as discussed in §2.2, we can indirectly obtain the leakage map by measuring their power spectral density. The resulting M𝑐𝑠 represents, for each core, the locations and conditions under which interference from other cores is minimized, thereby enabling fine-grained per-core probing. Although M𝑐𝑠 -guided probing significantly reduces interference from neighboring cores, it does not completely eliminate it. Nevertheless, the residual interference can be effectively mitigated by the Adaptive Interference Suppression (§3.4), which leverages sideband characteristics for adaptive suppression. Note that the M𝑐𝑠 needs to be derived only once per device type and remains valid across all devices equipped with the same chip.

3.3

Inter-Core Signal Harmonization (ICSH)

ICSH minimizes signal heterogeneity as a prerequisite for both Adaptive Interference Suppression (§3.4) and Core-Agnostic Architecture (§3.6). The key idea of this approach is to harmonize signal

Target Device

SuperSpeed USB

𝑳𝒄𝒐𝒓𝒆𝟐 𝑳𝒄𝒐𝒓𝒆𝟑

Modeling Phase : ❶ → ❷ → ❸ →❹ → X Monitoring Phase : X → ❷ → ❸ → X → ❺

Demodulation & FFT

𝑳𝒄𝒐𝒓𝒆𝟏

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Core-Agnostic Dataset

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❸ ❸

❸ Multi-Channel Signal Acquisition & Pre-Processing (All channels synchronized) Down Conversion

❷ High-Precision Per-Core Probing

❹ High-Coverage Spectral Modeling Pre-Processing (Block ❸)

Pipelined implementation on FPGA

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PC / Laptop

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Metric (Reconst. Err.)

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Prototype Device Localized Per-Core EM Leakage

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Pre-characterized params.

❶ Core Selection Map Derivation

Daehyeon Bae, Sujin Park, Insup Lee, Younggiu Jung, Kyeongsik Lee, HeeSeok Kim, and Seokhie Hong

𝑆

Adaptive Interference Suppression

Detection Criteria

DAC ’26, July 26–29, 2026, Long Beach, CA, USA

Pre-trained Model All cores monitored by a single reference model (cf. CAA).

Figure 3: High-level representation of the proposed method. Block ❸ operates on a fully pipelined and channel-synchronized device. Algorithm 1: Core Selection Map derivation. Input: Leakage Maps ( M𝐿 ), Upper bound of inter-core interference (𝛼 1 %), Lower bound of desired signal (𝛼 2 %), Minimum valid pts per cluster (𝛽 ), Scoring weight (𝑤 ) Output: Core Selection Map ( M𝑐𝑠 )

C ← [] // Result candidates 2 for all (setup_id, core_id) in M𝐿 do 3 M𝑡 ← M𝐿 [ setup_id ] [ core_id ] // Map of target core 4 M𝑜 ← M𝐿 [ setup_id ] [≠ core_id ] // Maps of other cores 5 for 𝐼𝑢𝑝𝑝𝑒𝑟 ← 0 to 𝛼 1 ; 𝑆𝑙𝑜𝑤𝑒𝑟 ← 𝛼 2 to 100 do 6 P𝑠𝑖𝑔𝑛𝑎𝑙 ← All points such that M𝑡 > max( M𝑡 ) · 𝑆𝑙𝑜𝑤𝑒𝑟 7 P𝑐𝑙𝑒𝑎𝑛 ← All points such that M𝑜 < max( M𝑜 ) · 𝐼𝑢𝑝𝑝𝑒𝑟 8 Extract common points from P𝑠𝑖𝑔𝑛𝑎𝑙 and P𝑐𝑙𝑒𝑎𝑛 9 if DBSCAN_validate_cluster( P𝑟 , 𝛽 ) then 10 score ← 𝑆𝑙𝑜𝑤𝑒𝑟 − 𝑤 · 𝐼𝑢𝑝𝑝𝑒𝑟 11 Append (core_id, setup_id, P𝑟 , score) to C 1

return argmax-score tuple for each core in C

Algorithm 2: Baseline Adjustment Offsets calculation. Input: Reference core (𝑐𝑟𝑒 𝑓 ), Other cores ( C𝑜𝑡ℎ𝑒𝑟𝑠 ), Number of spectra for averaging (𝑁𝑠𝑝𝑒𝑐𝑡𝑟𝑎 ) Output: Gains ( G ), Baseline Adjustment Offsets ( O ) Run gadget on 𝑐𝑟𝑒 𝑓 𝑆𝑟𝑒 𝑓 ← Sweep and averaging 𝑁𝑠𝑝𝑒𝑐𝑡𝑟𝑎 spectra // Reference spectrum 3 Stop gadget on 𝑐 𝑟𝑒 𝑓 4 𝜂𝑟𝑒 𝑓 ← Calculate baseline level 5 for each 𝑐 in C𝑜𝑡ℎ𝑒𝑟𝑠 do 6 Run gadget on 𝑐 7 D ← [] // Result candidates 8 for each g in available gains do 9 Set gain 𝑔 to channel 𝑐 10 𝑆𝑔 ← Sweep and average 𝑁𝑠𝑝𝑒𝑐𝑡𝑟𝑎 spectra 11 𝜂𝑔 ← Calculate baseline level 12 𝑑 ← Euclidean dist. between 𝑆𝑟𝑒 𝑓 − 𝜂𝑟𝑒 𝑓 and 𝑆𝑔 − 𝜂𝑔 13 Append (𝑑 , 𝑔, 𝜂𝑔 ) to 𝐷 1 2

Stop gadget on 𝑐 Append g and 𝜂𝑔 of argmin d in D to G and O , respectively

14 15

mov x1 , #0 x f f f f f f f f f f f f f f f f mov x2 , #0 x f f 1 1 gadget : u d i v x0 , x1 , x2 b gadget

Figure 4: Gadget for BCM2711 designed to induce artificial spectral leakage. The gadget repeats every 17 cycles, creating artificial peaks at 𝑓clk ±𝑛· 𝑓clk/17, where 𝑓clk denotes the clock frequency and 𝑛 ∈ N.

levels and spectral baselines (noise floors) by adjusting other channels to match a designated reference channel (core). To this end, Algorithm 2 is used to derive the optimal gains that produce similar signal levels, as well as the Baseline Adjustment Offsets that characterize deviations in the noise floor. During this process, a gadget is also employed to artificially generate Type-2 sidebands serving as a reference. Subsequently, the signal levels and baselines of the spectra are harmonized in real time on the prototype device.

3.4

Adaptive Interference Suppression (AIS)

The degree of interference from neighboring cores varies significantly depending on their activity—i.e., the type of sidebands (§2.3). Among these, we focus on Type-2 sidebands, which constitute the dominant interference component, as supported by Parseval’s theorem. That is, although different CPU activities produce different EM leakage patterns, the overall energy (L2 norm) remains largely consistent across types—both in time and frequency domains. Type-2 activity, however, concentrates energy into a few discrete peaks

return G, O

producing strong interference that is clearly visible to neighboring cores. In contrast, other types disperse energy more broadly, causing interference sidebands to be buried in the noise floor. Per-core signals can be simultaneously acquired with perfect synchronization, enabled by the prototype device (refer to §4.1). Accordingly, the key idea is to adaptively estimate and suppress inter-core interference on a per-frame basis. To this end, we first derive an Interference Matrix that characterizes the degree of leakage coupling between all cores using Algorithm 3. A gadget is also used in this step, as in ICSH , and the same one can be reused. Each value in the Interference Matrix denotes the ratio of sideband magnitude between neighboring-core activity and self-core activity, ranging from 0 (none) to 1 (strong interference). Algorithm 4 then performs in-line interference suppression on the prototype device based on the derived Interference Matrix. To ensure that only genuine interference is removed, the procedure must be applied in the order of cores that are least affected by others.

3.5

High-Coverage Spectral Modeling

To model the sidebands of the EM leakage arising from the primitives introduced in §2.2, we adopt a signal-centric approach that avoids intermediate abstractions—such as state information [34, 39]—often employed in prior work. That is, we learn only the inherent patterns of the signal and detect anomalies as deviations

Exploiting Per-Core Leakage: Electromagnetic Side-Channel Monitoring of Multicore Architectures

DAC ’26, July 26–29, 2026, Long Beach, CA, USA

Laptop

Probe Station Near-Field Probes

Bias Tees

Near-Field Probes

Target Device

(For probe power supply)

Prototype Device

RF Front-End (ADI FMComms5)

Carrier Board

USB 3.0 Connection

(ZCU102 / Zynq MPSoC)

(USB 3.2 Gen 1x1)

(a) Experimental setup with the prototype device

(b) Per-core probing

Figure 5: Experimental setup of the proposed method. The probe station is used for M𝑐𝑠 derivation. Algorithm 3: Interference Matrix generation. Input: Number of spectra for averaging (𝑁𝑠𝑝𝑒𝑐𝑡𝑟𝑎 ), Available CPU cores ( C𝑎𝑙𝑙 ), Gains from ICSH ( G ) Output: Interference Matrix (𝑀 ) Set per-channel gains from G for each 𝑐𝑖𝑛𝑡 𝑓 in C𝑎𝑙𝑙 do 3 Run gadget on 𝑐𝑖𝑛𝑡 𝑓 4 S𝑖𝑛𝑡 𝑓 ← Sweep and average 𝑁𝑠𝑝𝑒𝑐𝑡𝑟𝑎 spectra on 𝑐𝑖𝑛𝑡 𝑓 5 𝜌𝑖𝑛𝑡 𝑓 ← Calculate signal level of S𝑖𝑛𝑡 𝑓 6 for each 𝑐 𝑣 in C𝑎𝑙𝑙 excluding 𝑐𝑖𝑛𝑡 𝑓 do 7 S𝑣 ← Sweep and average 𝑁𝑠𝑝𝑒𝑐𝑡𝑟𝑎 spectra on 𝑐 𝑣 8 𝜌 𝑣 ← Calculate signal level of S𝑣 9 𝑀 [𝑐𝑖𝑛𝑡 𝑓 ] [𝑐 𝑣 ] ← 𝜌𝑖𝑛𝑡 𝑓 /𝜌 𝑣 // Interference ratio

1 2

Stop gadget on 𝑐𝑖𝑛𝑡 𝑓

10 11

return 𝑀

Algorithm 4: In-line interference suppression. Input: Interfering core spectrum (𝑆𝑖𝑛𝑡 𝑓 ), Neighboring core spectra ( S𝑣𝑖𝑐𝑡𝑖𝑚𝑠 ), Interference Matrix (𝑀 ), Adjustment factor (𝛾 )

𝑖𝑚𝑎𝑥 ← max(𝑆𝑖𝑛𝑡 𝑓 ) // Maximum interference magnitude for each 𝑆 𝑣 in S𝑣𝑖𝑐𝑡𝑖𝑚𝑠 do 3 𝜄 ← Corresponding interference ratio from the 𝑀 4 𝑡ℎ𝑠𝑢𝑝 ← 𝑖𝑚𝑎𝑥 · (1 − 𝜄 + 𝛾 ) // Threshold 5 𝑆 𝑣 ← max(0, 𝑆 𝑣 − 𝑡ℎ𝑠𝑢𝑝 ) // Update 𝑆 𝑣 (intf. suppression)

must be used in conjunction with this architecture. This design ensures that task assignment and migration have no impact, and that the load-balancing policy no longer needs to be considered.

4 Implementation and Evaluation 4.1 Prototype Device The proposed method requires proportionally more RF channels and their associated resource demands—such as high data rates and throughput—which may cast doubt on its feasibility. In addition, the AIS requires perfect synchronization of signals across channels (cores). To address these concerns, we implement a prototype device for synchronized multi-channel signal acquisition and pre-processing. The prototype device consists of AMD’s ZCU102, a heterogeneous SoC platform based on the ZynqTM UltraScale+ MPSoC [5], and Analog Devices’ FMComms5, a four-channel RF front-end [6]. The core logic is implemented on the FPGA in a pipelined manner, as illustrated in Figure 3 (block 3 ). We also develop bare-metal firmware for a Cortex-A53 core in the Zynq MPSoC, handling RF transceiver control and high-bandwidth USB communication (USB 3.2 Gen 1x1, up to 5 Gbps).

4.2 from this learned behavior. To this end, we adopt an unsupervised vanilla autoencoder as the backbone, owing to its simplicity, high throughput, and proven effectiveness in anomaly detection [12]. We train the autoencoder to minimize the reconstruction error of individual FFT frames, where frames with high reconstruction errors—reflecting unlearned patterns—are identified as anomalies during inference. Although state-of-the-art architectures such as Transformers [37] offer greater modeling capacity, their inference latency and resource demands render them impractical.

3.6

Experimental Setup

We use a Raspberry Pi 4B [33] equipped with a Broadcom BCM2711 SoC integrating four ARM Cortex-A72 cores as our target platform. It runs on Raspberry Pi OS Lite (Linux kernel 6.12.25) with a command-line interface. The device operates at a fixed clock frequency of 600 MHz without DVFS. In all experiments, we use the prototype device to acquire per-core leakage signals with the center frequency set equal to the clock frequency and a sampling rate of 10 MS/s. Each core is probed using high-resolution near-field probes—Langer MFA-R 0.2–6 and MFA-R 0.2–75 (Δ=300 𝜇𝑚)—based on the M𝑐𝑠 derived in §4.3. We also use the Riscure probe station to obtain the M𝑐𝑠 . The experimental setup is shown in Figure 5.

Core-Agnostic Architecture

This approach is an architecture for modeling and monitoring percore signals that addresses dynamic core assignment and pursues structural simplicity. The main idea is to eliminate the structural boundaries across cores, as illustrated in Figure 3 (block 4 and 5 ), where a single reference model is used regardless of the number of cores. However, given the heterogeneous nature of per-core signals and the presence of inter-channel measurement variation, ICSH

4.3

Per-Core Distinguishability

Using four different setups, we measure all four cores of the BCM2711 to obtain 16 per-core maps; these maps are shown in Figure 6 and constitute the M𝐿 , from which the M𝑐𝑠 is derived using Algorithm 1 (Figure 7(a)). We also present the Interference Matrix in Figure 7(b). As described in §3.4, interference suppression proceeds in the order of cores least affected by neighboring activity—Core 1→3→0→2.

Setup 4 (135°)

100

Core 1

100

Core 2

100

80 0

100

Core 3

Reconst. Err.

Setup 3 (90°)

0 20

Reconst. Err.

Setup 2 (45°)

0 20

100

Figure 6: Leakage maps acquired from the four cores of the BCM2711 under four distinct probing setups (angles). Measurements were performed by scanning the surface with a 300 𝜇𝑚-resolution coil positioned vertically to the die.

Y offset

Core3

Core2

Setup: 45° Score: 95.5

Setup: 135° Score: 95.6

40 60 80

100 0

Core1

Core0

Setup: 0° Score: 85.4 20

Setup: 45° Score: 94.3

X offset

100

(a) Core Selection Map ( M𝑐𝑠 )

Core0

N/A

0.43

0.24

0.19

0.287

Core1

0.20

N/A

0.20

0.21

0.203

Core2

0.45

0.24

N/A

0.32

0.337

Core3

0.19

0.33

0.26

N/A

0.260

Core1

Core2

Core3

Average

Core0

Interfering Cores

(b) Interference Matrix

Figure 7: Core Selection Map and Interference Matrix derived from Algorithm 1 and Algorithm 3 using parameters 𝛼 1 =15%, 𝛼 2 =80%, 𝛽=5, 𝑤=3, and 𝑁𝑠𝑝𝑒𝑐𝑡𝑟𝑎 =1000.

0 20

×10 5

Monitoring on Core1

×10 5

Monitoring on Core3

10 0

Monitoring on Core2

×10 5 5

Time (s) / 146,484 Frames

AUC with respect to SMA 1

Interference Matrix

Victim Cores

Core Selection Map (Mcs)

Monitoring on Core0

×10 5 10

Figure 8: Per-core monitoring results on BCM2711 (SMA=15 ms). Green: benign behavior observed on the same core used during modeling (C0: Susan, C1: Basicmath, C2: MLP, C3: AES); Blue: benign behavior under a remapped core assignment (C0: AES, C1: MLP, C2: Susan, C3: Basicmath); Red: anomalous behavior sequentially injected into Core0 through Core3 (PoC anomalous behavior: find).

AUC (logit scale)

Core 0

Setup 1 (0°)

Daehyeon Bae, Sujin Park, Insup Lee, Younggiu Jung, Kyeongsik Lee, HeeSeok Kim, and Seokhie Hong

1 10 3

0.995 0.99

1 10 2 1

0.95

10 1 1 2 0

1.0

Core0 Core1 Core2 Core3

10 4

0.8 5

SMA length (ms)

True Positive Rate

DAC ’26, July 26–29, 2026, Long Beach, CA, USA

ROC Curves (FPR<0.01)

0.8 0.6 0.4 Core0 Core1 Core2 Core3

0.2

0.0 0.000 0.002 0.004 0.006 0.008 0.010

False Positive Rate

Figure 9: Monitoring performance (AUC) with respect to SMA length and the corresponding ROC curves at SMA=15 ms, where all cores achieve an AUC above 0.995.

Discussion

Since DPP requires high-precision physical positioning, the setup process tends to be both costly and cumbersome, and prone to spatial deviations. This issue can be mitigated by employing customAcquiring the 16 leakage maps takes approximately 10 hours, while built high-precision probes with handcrafted coils [16, 21, 27, 28, 32], Algorithm 1 completes in about 15 minutes (spatial granularity=101×101). as well as a harness designed based on M𝑐𝑠 . In addition, repeatedly As noted in §3.2, the Core Selection Map is derived only once per opening the device enclosure for each monitoring cycle is inefficient device (or chip) type; thus, its duration does not hinder the feasibiland may raise compliance issues—particularly in systems subject ity. Figure 5(b) shows the high-precision multi-probing setup based to electromagnetic compatibility (EMC) [2] or military standards on the M𝑐𝑠 . such as MIL-STD-461 [1]. This issue can be mitigated by designing the target system with signal measurement ports at the enclosure 4.4 Per-Core Monitoring: Leakage Exploitation level, considering EMI shielding when required; the measurement setup can then be completed simply by connecting the instrument We define four software tasks as benign, taking into account the to external ports of the enclosure, assuming that internal probing characteristics of embedded systems, and execute them in paralis performed via a harness. lel on each core. These include an MLP inference engine and an AES encryption module, reflecting trends in edge computing, as 6 Conclusion and Future Work well as basicmath and susan from MiBench [19], which are widely adopted embedded benchmarks in side-channel monitoring literaThis work, for the first time, unveils the EM leakage mechanisms ture. We also model FFT frames of approximately 0.2 ms in length of multicore architectures and establishes the feasibility of perusing an autoencoder with a 2048–700–300–700–2048 architecture. core leakage exploitation. Building on these findings, we develop Figure 8 presents the results of sequentially triggering an undefined a prototype that implements a side-channel monitoring method anomalous behavior on Core0 through Core3 while benign tasks for multicore systems and validate its effectiveness on an off-theare running concurrently on all cores. To demonstrate core-agnostic shelf quad-core embedded platform. By enabling per-core leakage monitoring, we also evaluate cases where the benign software is exploitation—previously considered infeasible—these results are executed on cores different from those used during modeling (blue). expected to facilitate broader EM-based side-channel analysis on Figure 9 illustrates the monitoring performance in terms of area unmodern multicore platforms. Future work includes enhancing the der the curve (AUC) as a function of simple moving average (SMA) proposed side-channel monitoring method, extending support to length and the receiver operating characteristic (ROC) curves at DVFS-capable systems, and integrating inference models into the SMA=15 ms, where all cores achieve an AUC above 0.995. FPGA fabric to achieve full end-to-end execution on the prototype.

Exploiting Per-Core Leakage: Electromagnetic Side-Channel Monitoring of Multicore Architectures

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