Analog-DB: An Agent-First Analog Integrated Circuit Database, From Blocks to Systems

ANALOG-DB: AN AGENT-FIRST ANALOG INTEGRATED CIRCUIT DATABASE

1

Analog-DB: An Agent-First Analog Integrated Circuit Database, From Blocks to Systems

arXiv:2609.01286v1 [cs.AI] 1 Sep 2026

Danial Noori Zadeh

and Mohamed B. Elamien

devices form a cascode current mirror rather than a simple one, which stage sets the gain, or which path closes a feedback loop. A fully differential OTA may combine several stages, each with its own compensation architecture, common-mode feedback network, and bias network, and space limits keep most papers from publishing the full working circuit [7], let alone the reasoning that names its parts. The omission compounds up the hierarchy: once that OTA is embedded in an instrumentation amplifier, a low-dropout regulator, or an analog-to-digital converter, system-level papers treat it as a solved sub-block. Fan et al., for instance, report a capacitively coupled chopper instrumentation amplifier (CCIA) for wireless sensor nodes and publish block- and simplified transistor-level schematics, but not the device sizes, bias values, or testbenches behind the reported numbers [8]. A later designer can cite that amplifier but cannot rebuild it. The same gap afflicts verification. A digital block travels with checks that are themselves readable: assertions and expected logic waveforms state a pass condition. Verifying an analog block instead requires measurement recipes over continuous waveforms, in which the stimulus, the corner, the extraction, and the threshold separating pass from fail are each a separate, unrecorded decision. The reader thus receives the achieved Index Terms—Electronic Design Automation, Analog IC Design, performance figures, but not the procedure that measured them. Open-Source PDK, Design Reuse, LLM Agents, Capacitively The second barrier is contractual: the artifacts that would Coupled Instrumentation Amplifier, Low Dropout Regulator, make a published result checkable are the ones an author may Biomedical Frontend, Design Benchmarks. not release. Foundry non-disclosure agreements encumber the process models a design depends on, so authors can publish I. I NTRODUCTION neither the exact netlist nor the simulation results behind a NALOG integrated circuits are essential to systems as reported number, although recent work proposes frameworks far apart as high-bandwidth memory interfaces [1], radio- for secure redaction of such NDA-encumbered information [9]. frequency transceivers, and low-power biomedical interfaces, Both barriers are answerable now in a way they were not from neural-recording front ends [2] to wearables [3]. Yet a decade ago. Open process design kits (PDKs) have made industry and academia have automated digital blocks far more a growing class of designs freely simulable (§II): a designer successfully than analog ones. Part of the difficulty is that who releases against such a kit hands the reader a circuit an analog block’s performance rests on tradeoffs among gain, they can run. This removes the contractual barrier but not the bandwidth, dynamic range, noise, power, and area [4], [5], representational one, since nothing in a process kit records [6]: no circuit is best on all of them at once, only best for how a published circuit is organized or under what testbench a target application. A designer explores these manually and its numbers were obtained. The field gained a process to share reports the final numbers. Analog design, unlike digital, still against; it still lacks a place to put the designs. has no common way to share these circuits together with the A second opportunity comes from language-model agents, testbenches that validate them; two structural barriers explain now applied to analog sizing, topology selection, and subwhy. circuit identification [10], [11], [12]. Such an agent needs The first barrier is representational: a netlist carries connec- an engineered context: a hierarchical design together with tivity, not intent. Subcircuits nest to any depth, so hierarchy the testbench that exercises it and the recorded result that itself is expressible; what no released artifact states is which says what it achieved. The three together let an agent reason about topologies and judge whether a candidate improves on The authors are with the Department of Electrical and Computer Engineering, what already exists, and no released corpus we are aware of McMaster University, Hamilton, ON, Canada (e-mail: noorizad@mcmaster.ca, dnoorizadeh@gmail.com; elamienm@mcmaster.ca). supplies all three in one artifact (§II). This demand motivates Abstract—Sharing analog integrated circuit designs remains difficult: foundry non-disclosure agreements restrict the process details a design depends on, and the testbenches behind published results are rarely released. We present analog-db, an open-source, versioned database built on a shareable design representation. A domain-specific language captures each design as a processneutral topology, reusable testbenches, and a machine-readable datasheet under one schema, so a design is shared in full and re-simulates on the process kits it is bound to. A parameterization scheme exposes functional sub-blocks and device sizes as named parameters that carry their matching constraints, making circuits composable and retargetable; a schema-governed contract and queryable catalog let AI design agents discover and reuse them directly. Across the regulator corpus, all 23 circuit-kit bindings on three open kits meet their own recorded specification bands (typical corner, matched devices, no layout) and 10 of 23 meet a common class band. Seventeen of the 23 imported sizings failed their testbenches and closed under a gm /ID sizing loop driven by the annotated sub-block roles, typically within one to three iterations. In a supervised case study, a coding agent working from the released artifacts sized the op-amp cores of a chopper instrumentation amplifier on an open 130 nm kit, locating four hand-entry defects and a missing common-mode feedback loop that the sizing-only baseline did not repair. The database holds 68 circuits across sixteen classes, verifiable at schematic level under a tiered harness and tracked on a power/performance scoreboard, released at https://github.com/MacAnalog/spicexplorer-release.

A

ANALOG-DB: AN AGENT-FIRST ANALOG INTEGRATED CIRCUIT DATABASE

GET class=<amplifier> external knowledge base

GET circuit=amp-029

Analog-DB Filesystem

Circuit Entry: amp-029

catalog.json

shared/Template/ database

<id>/pdk/<pdk-id>/ corners.yaml devices.map.yaml sizing.yaml netlist.{spice/sc}

group: Current Mirror simple.{pmos/nmos} wilson.{pmos/nmos} high-swing.{pmos/nmos}

datasheet.yaml defines... Default Achieved metrics*

Simulate params=<sizing.yaml>

Simulator

Netlist View Spectre/NgSpice

Metric Extraction Block Detection

group: Compensation miller

scoreboard/<pdk>/ <design-point-id>.json Open PDK Environment Translator

testbench-templates/* datasheet-defaults.yaml metrics.yaml

Design Params PPA: Power Consumption Performance Area

analysis.yaml ac_open_loop.yaml cmrr.yaml dc_op.yaml noise.yaml linearity.yaml params.yaml defines... Components Tie Groups Geometry

IHP-130.yaml defines... corners device mapping geometry

ldo

... comparator ...

...

Spectre/NgSpice

amplifier

GF-180nm.yaml ...

...

design_rule.md

SpiceXplorer Core Functions

shared/PDK/ database

...

Coding Agent

shared/classes/ database

circuit.yaml

UPDATE Scoreboard

GET design-rule =<block>

2

afe ...

Fig. 1. System overview. A design agent queries the catalog by class and accession identifier, retrieves an entry (topology, datasheet, analyses, parameters), and simulates it through the SpiceXplorer harness; entries draw on shared class definitions and process-kit registries. File labels in the drawing are illustrative rather than verbatim: the released kit registries are ihp-sg13g2, gf180mcu, and sky130; per-kit device geometry is stored in each entry’s sizing.yaml; and every released simulation runs on ngspice against the open kits (the other simulator lane shown ships kit-unbound).

the machine-actionability requirement of §III-A. vice sizes as named parameters carrying their matching constraints, making circuits composable and retargetable. One representation addresses both barriers: it separates what • An open, populated database. 68 verifiable circuits is shareable from what is encumbered and names the structure across sixteen classes, 65 of them carrying recorded design and acceptance conditions a netlist leaves implicit. We present points (schematic level, typical corner, matched devices) analog-db1 , an open-source, versioned database built on such (Table III), released as a versioned corpus that others can a representation. A design can then be released in full: a extend. reader who holds the relevant kit can re-simulate it directly, and one who does not can port it to a kit they own. Because the representation names a circuit’s sub-blocks rather than II. BACKGROUND AND R ELATED W ORK flattening them, that design can also be reused inside a larger Existing efforts each supply part of what reuse demands, one rather than re-derived. Our contributions are as follows: and none supplies all of it in a released corpus. Generator • A foundry-neutral sharing method. A domain-specific frameworks bind a circuit to its own testbench and measurement language that captures each design as a PDK-neutral managers and carry them across processes, but they distribute topology, a reusable testbench, and a machine-readable generators rather than a curated, queryable corpus with recorded datasheet under one schema and carries no proprietary acceptance criteria [13]. PDK-neutral intermediate represenprocess detail, so a design can be released in full, retations give the topology a schema and put the analyses in simulated directly on any kit it binds, and retargeted to the same object model, across the same open kits used here, another by adding one binding. without shipping designs, results, or structural annotation [14]. • An agent-first, human-readable interface. A schemaStructural annotation of flat netlists is an established line of governed contract and a queryable catalog addressable its own, by exact subgraph isomorphism, by learned models, by AI design agents without a service, paired with autoand by library-free bottom-up construction, but it operates on generated schematic views of the same entries. netlists the user supplies rather than on a released corpus that • A portability and verification path. Automatic lowering carries its annotations as part of the record [15], [16], [17]. to multiple open PDKs as verified SPICE decks, crossBenchmark corpora release circuits at far larger scale than this PDK retargeting, a tiered verification harness, and a work, one with recorded simulated results [18], the other drawn power/performance scoreboard (with the gate-area proxy from the literature without testbenches [19], and testing suites of §III-C), so a released design carries a checkable status release circuits with shared testbenches on an open kit [20], but and can be retargeted to the process the reader has. none of them records per-circuit acceptance bands, hierarchy, • A sub-block annotation and parameterization scheme. or a machine-readable contract. The contribution of analog-db An annotation of each design’s detected functional subis the integration: one versioned corpus in which the topology, blocks (current mirrors, differential pairs, cross-coupled the testbench, the acceptance band, the recorded outcome, and loads; 51% of corpus devices at the archived revision) the structural annotation are the same object, addressable by an alongside a complete parameterization that exposes deagent without a service. Table I compares the closest efforts. AnalogGym [20] is the closest testing suite. It ships 30 1Written analog-db throughout, after the released artifact’s name; the title’s Analog-DB is the same name capitalized. topologies in five categories, two shared testbench templates

ANALOG-DB: AN AGENT-FIRST ANALOG INTEGRATED CIRCUIT DATABASE

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TABLE I ANALOG - DB AGAINST THE CLOSEST RELEASED ARTIFACTS . E ACH CELL STATES WHAT THAT SYSTEM SHIPS AS RELEASED , TAKEN FROM ITS PUBLICATION AND PUBLIC REPOSITORY; “–” MARKS A CAPABILITY IT DOES NOT PROVIDE .

System

Unit of release, scale

Testbenches shipped

AnalogGym [20]

Testing suite; 30 topologies, 5 categories; 2 of 5 categories run open-source on the bundled sky130 kit RL sizing flow; 1 topology (folded cascode) on an open kit Topology dataset; 10,000 behavioral op-amps

Yes: 2 shared templates, Sizing-method baselines; Flat netlists; no composi- – amplifier and LDO only no per-circuit acceptance tion bands

CORAOpAmp [21] OCB [18] AMSnet 2.0 [19] AMSSizingBench [22] Masala-CHAI [23] AnalogGenie [24] BAG2 [13] VLSIR [14] analog-db work)

(this

Yes, its one topology

Recorded results, accep- Structure, hierarchy tance bands

Single design point

Generation and evalu- Simulated results; no acation harness; no per- ceptance bands circuit testbench Schematic/netlist database; – – 2,686 circuits from the literature Sizing benchmark; 24 Simulator-based evalua- Per-circuit spec threshAMS circuits on SKY130 tion under stated con- olds; no recorded design straints points Netlist dataset; 7,500 – Netlist-level verification; schematics from 10 no recorded performance textbooks – Generative topology en- – gine with its training dataset Generator framework; no Generator-embedded Re-measured per instantifixed corpus testbench and ation; no released corpus measurement managers of outcomes PDK-neutral IR with pub- Analyses in the same ob- – lished open-kit packages ject model

–

Machine contract

–

Graph encoding of each – topology Schematic-netlist corre- – spondence –

–

Schematic-netlist corre- – spondence Sequence-based representation

graph

Hierarchical generators

– Programmatic API

Schema-governed hierar- Protobuf schema chy

Versioned corpus; 68 cir- Yes: 65 of 68 circuits Recorded design points Detected sub-blocks; Schema-governed file cuits, 16 classes, 3 open bind class-owned tem- judged against per-metric composition closed over contract + catalog kits plates; 3 fall outside specification bands entries thema

a The ideal-amplifier programmable-gain stage (ia_005) and the binary capacitor bank (sw_003) have static code pins outside the class port contract, so

their measured values are recorded in the datasheet without a bound bench (Table XIII); the line driver (drv_001) binds self-contained testbench decks through the optimizer projection instead of class templates.

that cover its amplifier and low-dropout-regulator categories, one uniform extraction script over AC, DC, and transient measures, and a bundled sky130 kit on which two of the five, the amplifiers and regulators, run open-source as distributed; the sensing-front-end, voltage-reference, and phase-locked-loop categories ship no open-source-runnable decks. What it does not record is what reuse needs next: no noise, distortion, or intermodulation analyses, no per-circuit acceptance bands, no way for one block to compose into a larger one, and no machine-readable contract. CORA-OpAmp [21] shows that a reinforcement-learning sizing loop can be made reproducible on an open PDK, but at a narrow scope: it targets a single folded-cascode topology and drives the simulator through scripting written for that topology. Three recent dataset efforts push scale on complementary axes, and each stops short of a different part of what reuse needs. AMS-SizingBench [22] releases 24 mixed-signal circuits on SKY130 with per-circuit specification thresholds and a simulator-in-the-loop harness, but the thresholds ship without recorded design points that meet them, and no entry composes into a larger one. MasalaCHAI [23] extracts 7,500 textbook schematics into verified SPICE netlists, two orders of magnitude beyond the corpus released here, but its unit of release is the bare netlist: it ships without testbenches, recorded results, or a machine

contract. AnalogGenie [24] generates circuit topologies over a sequence-based graph dataset, and the generated artifact is again connectivity alone rather than a verified, benched entry. Teaching corpora such as Pretl’s analog circuit design collection [25] publish worked designs on the same open tools, but as course material rather than as a verified, queryable corpus. Adjacent open-source flows automate complementary stages of the same pipeline: OpenFASoC generates mixedsignal blocks end to end [26], ALIGN automates analog layout [27], AnalogCoder generates topologies with language models [28], and AICircuit benchmarks learned sizing across circuit levels [29]. Automated analog design predates language-model agents by decades. A long line of work drives sizing with evolutionary and Bayesian search, much of its methodological effort spent shaping cost functions and handling constraints across competing metrics [30], [31], [32], [33], [34], and symbolic analysis explores topology choices analytically [35]. Crossnode re-sizing is likewise an established subfield: constantinversion-level resizing rules [36] are in substance the gm /ID preserving retarget this work applies per detected role (§III-C). Language models extend the annotation line, identifying the functional sub-blocks of a flat netlist [12], a problem analogdb’s deterministic template matching addresses at release

ANALOG-DB: AN AGENT-FIRST ANALOG INTEGRATED CIRCUIT DATABASE

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time (§III-B2). Agent-driven sizing flows, meanwhile, already Algorithm 1 Sub-block detection by labeled subgraph matchpresuppose a corpus of this kind. AnalogSAGE [10] and ing. HeaRT, a hierarchical circuit-reasoning agentic framework that Require: flattened design graph G; template library T (Table II) couples reasoning-tree agents with off-the-shelf optimizers, Ensure: block instances R; per-device structural roles evaluated on its authors’ 40-circuit benchmark of flattened 1: label every graph: nodes by device kind and polarity; SPICE netlists [11], both drive a simulator from an agent loop, edges by their gate/drain/source pin multiset, so a diode yet neither releases the designs or the testbenches it ran on. connection forms parallel edges; bulk pins only where a Each therefore assembles a private corpus that does not outlive template demands them the paper reporting it: a later agent can read the numbers 2: R ← ∅ but cannot re-simulate the flow that produced them. analog3: for all templates t ∈ T with graph Gt do db answers this demand by exposing every entry through a 4: for all label-preserving monomorphisms φ : Gt ,→ G schema-governed set of released files (§III-B6) that an agent do can query directly. if supply rails anchor as t demands and each 5: Open process design kits changed what a published analog internal net of t maps to a private net of equal degree result can carry with it: a design released against one is then simulable by any reader who downloads the kit, with no foundry 6: add block instance (t, φ) to R entitlement. An open kit, however, fixes only the model a 7: end if netlist is evaluated against, not the netlist’s own legibility. The 8: end for representation of §III-B supplies that missing layer and lowers 9: end for to the open kits, so its entries can be simulated with them. 10: on an equal device set, prefer a bulk-aware match to a bulk-blind one III. M ETHOD 11: assign each covered device the structural role its match A. Requirements for a Shareable Design Representation names 12: render the annotated and hierarchical views from R The two barriers of Section I translate directly into the first two requirements below. The remaining three follow from the opportunity that makes a shared corpus worth building, namely reuse across the design hierarchy and reuse by software a four-part object: a process-neutral topology T , a parameter agents. Together they define what a shareable analog design space Θ carrying the matching constraints among devices representation must satisfy, each addressed by the subsection (§III-B3), a behavioral contract C, and a set of per-process bindings B. The first three are detailed in the subsections that noted: follow. A binding b ∈ B supplies everything one process kit • R1: Foundry neutrality. A released design carries no requires: a mapping from generic device kinds to kit devices, foundry-encumbered process detail, yet remains simulable concrete sizing values with search bounds, and corner selections. through open process kits (§III-B2). Lowering is then a mechanical function • R2: Reproducibility. The testbenches, extraction recipes, and acceptance criteria behind every reported result travel L : (T, a, b) 7−→ decka,b , (2) with the design itself (§III-B4). where a ranges over the analyses the contract declares and b • R3: Structure over opacity. A design exposes its functional sub-blocks and its named parameters with their over the entry’s bindings, so the same entry yields one readymatching constraints, rather than an opaque flat netlist to-run SPICE deck per bound kit and analysis. Three further terms recur throughout the paper. A design (§III-B2, §III-B3). point is a recorded simulation outcome: one concrete sizing • R4: Composability. Verified blocks compose into larger of one entry on one kit, stored with its per-corner measured systems that are again verifiable entries of the same kind metrics and pass/fail verdicts under a content-derived identifier, (§III-B5). so every reported number remains reproducible from its record. • R5: Machine actionability. Every artifact is schemaA validated design point is a design point whose every specgoverned and queryable, so a software agent can discover, bounded metric passes, the T4 criterion of §III-C; the paper uses compare, and reuse designs with a verifiable status, while both terms in exactly these senses. An accession identifier is the same artifacts stay readable to human designers the stable, append-only name under which an entry is published (§III-B6). and cited. Throughout, artifacts that encode designer intent Section III-C then describes how generation and verification are authored and human-reviewed, while derived artifacts are keep R1 and R2 checkable for every released artifact. regenerated mechanically and checked against drift (§III-C). Figure 1 shows how an agent interacts with these pieces, and Appendix B gives the concrete syntax of each artifact on a B. The analog-db Design Representation 1) A Formal Model of a Design Entry: The unit of release worked example. 2) Separating Topology from Process: A circuit’s topology in analog-db is the design entry, can be stated without any process detail, and separating the E = (T, Θ, C, B), (1) two is what makes a design releasable (R1). In the abstract

ANALOG-DB: AN AGENT-FIRST ANALOG INTEGRATED CIRCUIT DATABASE

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netlist, every device is a generic token carrying only its kind every device geometry field, the symbol set Σ: a complete, and polarity, and every geometry field refers to a named symbol mechanical inventory of the design’s degrees of freedom. An rather than a number; nothing identifies a foundry device, model authored layer then declares how those symbols relate. Tie section, or corner library. All such detail enters through the groups induce the equivalence ∼, whose classes share a value: per-kit binding, so the released topology is free of foundry- a differential pair matches in full geometry; a mirror rail shares encumbered content. A reader who holds any bound kit obtains its length. Ratio declarations R freeze designed current gains a simulable circuit by lowering, while a reader who holds none as relations rather than free values. Individual parameters can also be frozen without being can still read, cite, and retarget the design. A flat netlist, however, satisfies R1 without satisfying R3. The removed from the record. The tie-group representatives left free representation therefore recovers the missing structure mechan- after ratios and freezes define the search space an optimizer may ically, by labeled subgraph matching of a functional template explore, and each per-kit binding assigns them a default value library against the flattened design graph (Algorithm 1). Each and a search band in that technology. Matching constraints match assigns the covered devices a deterministic structural are therefore stored with the design as explicit, reviewable role, and the assigned roles drive two generated views of the statements (R3); Appendix B (Listings 1 and 2) shows both same entry: an annotated schematic in which detected blocks layers on a two-stage amplifier. 4) Executable Datasheets: Published performance tables appear as labeled groups, and a hierarchical view that draws one symbol per block. The functional organization that published seldom include the procedure that measured them; the datasheet netlists leave implicit (§I) thus becomes part of the released makes that procedure part of the design (R2). The contract C record, and the generated views keep the entry legible to human of (1) assigns each reported metric m a triple (am , xm , Sm ): the analysis am that produces it, the extraction xm that reads designers. The matcher draws on a library of hand-authored functional a number out of the resulting waveforms, and the specification templates, one small netlist per structural variant, grouped by band Sm that separates pass from fail,
functional family in Table II. Current-mirror variants make up pass(m, b, c) ⇐⇒ xm simc L(T, am , b) ∈ Sm , (3) more than half the library because a mirror’s function is set almost entirely by its wiring topology [37], [38]. The library is where c ranges over the corner selections the binding b declares device-level at the archived revision. Common-mode feedback, and simc evaluates the deck at that corner. A design point which every fully differential design requires, enters the corpus records one verdict per declared corner, and every design by the representation’s other route: as released entries rather point at the archived revision evaluates the typical corner than as templates. The corpus carries a continuous-time 5T (§V-A). Analyses themselves instantiate class-owned testbench sense amplifier in each input polarity, a behavioral sense servo, templates at stated operating conditions, and the class registry and a discrete-time switched-capacitor detector (Table III), and also owns the canonical metric vocabulary, so a phase margin each of the five composites of §III-B5 closes its common- measured on one amplifier means the same bench, extraction, mode loop by instantiating one of them at a pinned design and conventions as a phase margin measured on any other. point. What no template yet recognizes is that same structure Because the verification harness and the results scoreboard sitting inline in a flat netlist, so the coverage statistics of §IV-A both judge against this one artifact, a reported number cannot attribute no role to it (§V-A). Matching semantics bound what disagree with the procedure that produced it. One caveat detection can claim, so this section states them exactly. The governs every measurement the contract produces: the release map φ of Algorithm 1 is an injective homomorphism that must simulates nominal schematics with perfectly matched devices, be induced on the template’s internal nets and boundary-free at so all reported rejection, offset, and residual-ripple figures are its terminals: an internal net of t must map to a private host net systematic CMRR/PSRR (mismatch excluded), the term used of equal degree. A template match therefore fails if any internal for them throughout. They are upper bounds on silicon, where net carries even one extra legitimate load, a strictness that keeps mismatch, which the current release does not model (§V-A), every emitted role exact but forfeits near-miss variants, and is sets these quantities. Listings 4 and 5 give the concrete form. one reason coverage stops at 51% (§IV-A). Matched instances 5) Hierarchical Composition: The step from blocks to may overlap on devices, as when one diode device anchors systems is a composition manifest: an authored declaration two mirror instances, but each covered device receives a single that builds a new circuit out of entries the database already recorded structural role. Subgraph isomorphism is NP-complete holds (R4). Each instance in the manifest names a block, pins in general; the template graphs are small and the kind, polarity, the exact revision of that block’s topology by content hash, and pin-multiset labels prune the search, so matching the full and wires its ports; the child’s released per-kit sizing supplies corpus completes as an ordinary step of release generation. its geometry on each kit the composite binds. The composite This deterministic, release-time annotation complements the may additionally expose an internal net of a block, remove a netlist-annotation line of [15], [16], [17], which recognizes block-local bias element it now supplies itself, or override a structure in user-supplied netlists at use time. block parameter; the instantiator owns the sizing of what it 3) Device Parameterization and Matching Constraints: composes. Reuse needs more than named device sizes: it also needs the Generation then flattens the manifest into an ordinary matching intent that a flat netlist discards. The parameter space netlist and sizing binding, so composition is closed over of (1) therefore has three components in two layers, Θ = entries: a manifest W over entries E1 , . . . , En yields (Σ, ∼, R). A generated layer assigns one symbolic variable to compose(E1 , . . . , En ; W ) = E ′ , again of the form (1). The

ANALOG-DB: AN AGENT-FIRST ANALOG INTEGRATED CIRCUIT DATABASE

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TABLE II S UB - BLOCK TEMPLATE LIBRARY AT THE ARCHIVED REVISION , GROUPED BY FUNCTIONAL FAMILY. T HE LIBRARY IS DEVICE - LEVEL THROUGHOUT; NO COMMON - MODE - FEEDBACK FAMILY EXISTS AT THIS REVISION (§III-B2). Group

Variants

Current mirrors

simple, cascode, Wilson, improved Wilson, high-swing cascode, improved high-swing cascode, low-voltage cascode, self-biased high-swing cascode, wide-swing [37], [38] simple, cascoded [37] simple, negative-resistance core [37] series, well and generator each independent or shared [39] bulk-blind, rail-tied-bulk transmission gate (complementary); differential chopper modulator (4× rail-tied-bulk pairs, same templates) complementary CMOS stack

Differential pairs Cross-coupled pairs Pseudo-resistors† Switches Inverter / push-pull stage

Templates

Total

18 4 2 4 2 1 31

† Partial catalog: the 4 series-symmetric cells of Fig. 3 in Guglielmi et al. are drawn and registered; the remaining 12 topologies of their §4 (single-cell

transdiodes, parallel-symmetric cells, linearity extensions, floating-voltage generators) are not yet templated.

Algorithm 2 Agent loop over the file contract: discover, compare, reuse. Require: the released catalog; a target class, kit k, and constraints 1: discover: filter the catalog to entries of the class whose ports and kit bindings meet the constraints 2: compare: rank the candidates on their recorded design points on k: spec verdicts, power, area, headline metrics 3: reuse: select an entry E = (T, Θ, C, B) with binding bk ∈ B and fetch its released decks L(T, a, bk ) 4: simulate, or re-size the free symbols of Θ within the bounds of bk and simulate again 5: judge every metric against the contract C; record the outcome as a new design point on the entry’s scoreboard

network access, or a running server (R5). Algorithm 2 states the loop this supports, and each pass through it leaves a new recorded design point behind for the next agent’s comparison to draw on. Append-only accession identifiers make every retrieved entry citable in later work. The same contract also serves human readers, because the generated views of §III-B2 keep every entry inspectable without running any tooling. A protocol wrapper is deferred as future work (§V-B): a convenience layer over the same files rather than new capability. C. Artifact Generation and Verification

The representation of §III-B is only as credible as the artifacts derived from it. This section states the guarantees the released database makes: derived artifacts are reproduced mechanically from the authored core, every entry carries a verification status with a defined meaning, process neutrality composite binds exactly the kits every child binds: writ- is demonstrated by porting rather than asserted, and what ′ ing T kits(B) for the kits a binding set covers, kits(B ) = simulation measures is retained as recorded design points rather than a single winner. i kits(Bi ) (each child instantiated at its pinned topology, with its released sizing on that kit). A kit some child does not bind is Lowering (2) resolves an entry’s neutral topology through unavailable to the composite until that child gains the binding. one of its bindings into ready-to-run simulation decks, so a The composite therefore carries its own datasheet, lowers to the reader reproduces a result by running a released deck rather than same kits, and passes through the same verification as any leaf by reassembling one. Retargeting synthesizes a new binding circuit, and no downstream tool treats hierarchy as a special from an existing one, extending the binding set B of (1) while case. Figure 2 shows the pattern on the chopper instrumentation T , Θ, and C stay fixed: devices and corners are re-mapped amplifier of [8], whose system-level entry composes the two op- onto the target kit and sizings clamped to its geometry rules, amp cores shown. Among the corpus’s five composites, another after which the new binding flows through the same lowering closes the common-mode loop of a fully differential two-stage and verification path as any other. Because a binding records amplifier with a feedback servo drawn from a separate entry only device and corner identifiers and geometry rules, and (Listing 8). A sub-block published this way supports more never model files, the entry itself stays free of process detail: than citation: the verified block can be instantiated in a larger what a new kit costs is a binding, not a rewrite. system at the design point where it was verified. “Verified” is a graded claim, and the database grades it 6) A Machine-Actionable Interface: An agent-facing corpus explicitly. Five tiers check progressively stronger properties. does not need a service; it needs a stable interface. The interface T0 checks schema validity; T1 checks that every derived artifact to analog-db is a file contract: the fixed set of files each entry regenerates byte for byte; T2 assembles every circuit, analysis, publishes, together with the schemas that govern them, as kit, and corner combination into a runnable deck; T3 simulates distinct from the per-entry behavioral contract C of (1). Every every released deck; and T4 checks the measured metrics artifact is governed by a versioned schema, and a generated against the datasheet’s specification bands, the pass predicate catalog summarizes each entry’s class, ports, kit bindings, and of (3). The first three tiers require no process kit and gate recorded results in a single queryable document, so any agent every change to the corpus. An entry’s published status is that can read files can use the database without credentials, named for the highest tier it passes: generated (T1), simulated

ANALOG-DB: AN AGENT-FIRST ANALOG INTEGRATED CIRCUIT DATABASE

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VDD PMOS bias sources (M1,M4)

Vb3

M1

M4

net1 net2

vin+

vin−

M3

M2

CMFB circuit (M5,M6,M7,M8,M15,M16)

von net6

M5

vref

M6

vop

M7

M8

net5 net4

Vb1

M9

M10 net3

Cascode diff pair (M2,M3,M9,M10)

vop

von Cascode load (M11,M12,M13,M14)

Simple mirror (M13,M14,M15)

Vb2

M11

M12

net7

M15

net8

M13

M16

M14

VSS Main OTA (telescopic cascode)

Common-mode feedback bias

(b) Ripple-loop integrator OTA

(a) CCIA system First stage (Gm1 ) – folded cascode

Second stage (Gm2 ) – CS stage VDD

Vb4 M7

M1

M6

M9

M8

PMOS bias sources (M1,M6–M9) net4

net5

voutp

net1

vinp

vinn

voutn

Vb3

M3

M2 Diff pair (M2,M3)

M10

M11 PMOS cascode (M6,M7,M10,M11)

net7 Cm1

Cm2

net6

M14 M13

M12

M15

net8

Vb2

net2 net3 NMOS bias sources (M4,M5)

net9

M5

M4

Vb1

VSS

(c) Two-stage chopper core Fig. 2. From blocks to systems: the chopper CCIA of [8] and its two op-amp cores, redrawn with functional groupings annotated. Groups matching a device-level template are matcher-detected: the differential pairs in (b) and (c) and the diode-referenced simple mirror in (b). The bias-source groups (current sources hung on the bias rails, with no diode reference in the drawn scope), the common-mode-feedback grouping, and the cascode-load grouping are designer annotations that the archived detection run does not emit (§V-A). A device may sit in two groups (in (b), M15 is both the mirror reference and part of the CMFB branch) while carrying one recorded role (§III-B2). (a) The system with its capacitively coupled feedback loops; (b) the ripple-reduction-loop integrator, a fully differential telescopic-cascode OTA with common-mode feedback; (c) the two-stage chopper-stabilized core (folded-cascode Gm1 , chopper, common-source Gm2 ).

(T3), validated (T4); validated is earned only when every specbounded metric passes. A baseline whose default sizing does not bias into a working circuit is recorded as the starting point for a search rather than as validated, so validated keeps its strict meaning. A separate structural check requires every released schematic to be graph-isomorphic to the netlist re-derived from it, so the generated views of §III-B2 can be trusted as views of the same circuit. Because an analog circuit meets a target application rather than a golden specification (§I), the scoreboard names no scalar best. Each simulation outcome can be recorded as a design point. For every circuit and kit, the scoreboard marks the Pareto front over power, area, and the headline metrics of the circuit’s class, with one named baseline per kit. Area is an acknowledged proxy: the summed gate area of the sized MOS devices, with

no spacing, routing, or well overhead, and with capacitors and resistors excluded. The passive exclusion matters: at typical metal-insulator-metal densities of roughly 1.5–2 fF/µm2 , a single 10 pF compensation capacitor occupies 5000–6700 µm2 , comparable to or exceeding the recorded gate area of many entries, so the proxy ranks device budgets rather than die cost. Because a new sizing extends the recorded tradeoff space instead of overwriting a winner, the corpus can serve as an optimization benchmark. Per-kit lookup tables for systematic transconductance-efficiency (gm /ID ) sizing [40], [41] and autogenerated optimizer configurations over the released decks [42], [43] provide the means of producing new design points, so an agent can size an entry against its own datasheet without authoring any testbench (exercised in §IV-D and Appendix A). The tables follow the pre-computed lookup-table method of

ANALOG-DB: AN AGENT-FIRST ANALOG INTEGRATED CIRCUIT DATABASE

TABLE III C IRCUIT COVERAGE BY CLASS . Class

Circuits

Amplifiers / OTAs Low-dropout regulators (LDO) Instrumentation amplifiers Support blocks Common-mode feedback (CMFB) Switches Temperature sensors Comparators ADC Line driver Sampler Trim Voltage reference

33 7 6 5 4 3 3 2 1 1 1 1 1

Total (verifiable)

68

The Support blocks row folds four small classes (5 circuits): support, buffer, differential pair, and gain stage.

8

TABLE IV V ERIFICATION STATUS BY CLASS , COMPUTED FROM THE RELEASED CATALOG AND SCOREBOARD : COUNTED ENTRIES , ENTRIES HOLDING AT LEAST ONE RECORDED DESIGN POINT, ENTRIES VALIDATED ( SOME RECORDED DESIGN POINT PASSES EVERY SPEC - BOUNDED METRIC , THE T4 CRITERION OF §III-C) ON AT LEAST ONE KIT, AND ENTRIES VALIDATED ON ALL THREE KITS . A LL VERDICTS ARE TYPICAL - CORNER .

Class Amplifiers / OTAs Low-dropout regulators (LDO) Instrumentation amplifiers Support blocks Common-mode feedback (CMFB) Switches Temperature sensors Comparators ADC Line driver Sampler Trim Voltage reference

With Validated All 3 Entries design pt. ≥1 kit kits 33 7 6 5 4 3 3 2 1 1 1 1 1

32 7 5 5 4 2 3 2 1 1 1 1 1

15 7 3 3 4 2 3 2 0 1 1 1 1

2 6 0 2 0 0 2 2 0 0 0 0 0

Jespers and Murmann, whose published starter kits already Total 68 65 43 14 sweep the same open kits [44], and are produced with an opensource implementation of that flow [45]; the archived revision records the tables for the representative device pairs on ihpsg13g2 and sky130 and regenerates the remainder mechanically classes and the table makes that unevenness inspectable rather from the released tools. than averaged away. A single automation layer drives generation, verification, Provenance is part of each record. Every entry names and simulation. Every simulation in this release runs on an the corpus or collection it came from, and 48 of the 68 open-source simulator (ngspice) against containerized open additionally cite the published design they realize; the collection process kits, so the whole flow is reproducible without a counts below sum to the corpus, while the citation count is commercial license. Continuous integration regenerates every smaller because not every collection entry realizes a single derived artifact on each change and rejects any drift, the published design. Twenty-two circuits are normalized from the mechanism behind the regeneration guarantee above. AnalogGym corpus [20], which contributes most of the threestage OTAs along with regulators and temperature sensors. IV. E XPERIMENTS Another 21 are hand-entered from published designs, among The evaluation asks five questions of the released arti- them the chopper instrumentation-amplifier family of Fan et fact, each answered by one subsection below: coverage and al. [8], the Hsu biomedical front end [46], [47], and the internal provenance (RQ1), reproducibility (RQ2), portability across amplifiers of a commercial buffered-reference regulator [48]. process kits (RQ3), whether the agent-first interface supports Five circuits come from Pretl’s teaching collection [25], one design work rather than retrieval alone (RQ4), and whether the from CORA-OpAmp [21], and five are composites of §III-B5, recorded design points are dense enough to expose performance authored in this work. The remaining 14 are drawn from tradeoffs and seed a sizing search (RQ5). other upstream sources or authored directly, with per-circuit provenance and licensing recorded in the release’s NOTICE file (Appendix C). A. Coverage and Provenance (RQ1) RQ1 tests the claims behind the populated database and the sub-block annotation scheme. At the archived revision the database holds 68 verifiable circuits across sixteen classes: 33 OTAs/op-amps, 7 low-dropout regulators, 6 instrumentation amplifiers, and smaller classes that range from common-mode feedback blocks to temperature sensors (Table III). Twenty-one of the 68 are fully differential, including four small blocks whose differential outputs are declared in their netlists rather than in the catalog summary. The count is conservative: it excludes three incomplete entries and the 13 reference circuits retained for provenance but never lowered. Table IV reports how far each class has been carried through the verification tiers of §III-C: 65 of the 68 entries hold at least one recorded design point, 43 are validated on at least one kit, and 14 on all three, so the corpus’s verification depth is uneven across

How much of each entry the representation explains is itself measured and released. Parameterization is complete: the generated layer names every geometry field of the corpus’s 1574 devices as a symbolic variable (3819 symbols on the representative kit, ihp-sg13g2), and the authored layer constrains that inventory: 1866 symbols are tied to a group representative through 444 tie groups, 255 are ratio-bound, and 365 are frozen, leaving 1333 free symbols to search. Twentytwo circuits also record structural symmetries left untied as reviewable warnings. Structural detection, by contrast, is partial. All 68 circuits carry generated structural views, spanning 1574 devices; the template matcher of §III-B2 assigns a functional role to 807 of them (51%), organized into 321 detected block instances. §V-A records the uncovered remainder as a limit of the current template library.

ANALOG-DB: AN AGENT-FIRST ANALOG INTEGRATED CIRCUIT DATABASE

9

B. Reproducibility (RQ2)

D. Agent Case Studies (RQ4)

RQ2 tests whether a reader can reproduce the released results from the released artifacts. Reproducibility rests on regeneration: simulation decks are derived mechanically from the authored core, and tier T1 of §III-C checks that they regenerate byte for byte, so the deck a reader runs is the one that produced the recorded design point. Two checks exercise this at the archived revision. First, every value in the benchmark tables of Appendix A is re-simulated from the archived database, except where a table footnote records otherwise; none is transcribed from a source publication. Second, a separate verifier audited the regulator study of §IV-D, re-running sixteen recorded circuit-kit baselines from the released sizing defaults rather than from the sizing sessions’ state, and reproduced every metric recorded for those sixteen bit for bit. Both checks demonstrate reproduction at the archived revision and the typical corner.

RQ4 tests the agent-first interface of §III-B6 and whether composition (R4) holds in use. We report two studies run as author-supervised sessions of a general-purpose large-languagemodel coding agent (Claude Code, running the Claude Opus 4.8 model). The session records identify the model only as Claude Opus 4.8 with the 1M-token context window; we did not capture the exact dated model version at the time, so the studies are reproducible in method but not bit-for-bit in agent behavior. In each study the agent sized database entries to their datasheets using the released artifacts and live simulation on each bound kit. The first subject is a buffered-reference low-dropout regulator bound to two process kits; the second is the chopper instrumentation amplifier of Fig. 2, carried from its op-amp cores to the closed system. Success is defined by the database’s own contract: a study is complete when every metric of the entry’s machine-readable datasheet passes under the class benches. Each accepted result re-enters the corpus as a recorded design point. The supervision protocol was interactive rather than autonomous: the author set each study’s objective, reviewed the agent’s proposed diagnoses and edits, and accepted or rejected results against the datasheet verdicts. Sizing values and the diagnostic probes that located each failure mechanism originated with the agent. Each study was recorded in a persession engineering report carrying every accepted number, root cause, and rejected repair. Neither those reports nor the full conversational transcripts are part of the release, and §V-A records that gap. No quantified per-intervention log was kept, so the studies claim feasibility under supervision, not autonomy. Each session ran the same loop over the released artifacts: re-simulate the imported sizing, so that every later claim is a delta against a reproducible baseline; localize the failure mechanism through the detected sub-block roles, the per-kit gm /ID tables, and targeted single-bench probes; re-size by converting per-role gm /ID targets to geometry through the same tables; and re-judge the full datasheet, accepting a trade only when the degraded metric still meets its specification. The regulator study applied this loop across the lowdropout corpus of Appendix A-B: seventeen of the twentythree imported sizings failed their benches, and the loop closed each, typically within one to three sizing iterations once a mechanism was identified. The buffered-reference regulator ldo_005 [48] (Fig. 3) concentrated the hardest failures: on gf180mcu the best sizing that satisfied every other specification still left a 519.5 mV dropout against the 400 mV bound, and the port to ihp-sg13g2 failed outright. Probing below the sizing layer exposed the shared cause, a netlist defect examined in Appendix A-B: a mirror gate rail with no DC definition of its own. A one-element repair that gives the rail a DC definition (the tie of Fig. 3), followed by a compensation retune, superseded both verdicts: the regulator passes all fourteen datasheet metrics on both kits (Table V), with dropout at 340 mV on gf180mcu and 170 mV on ihp-sg13g2. The instrumentation-amplifier study began one stage earlier, at bring-up: the system entered the database from hand-drawn schematics, and characterization exposed defects that had

C. Cross-PDK Portability (RQ3) RQ3 tests whether process neutrality (R1) holds in practice. The low-dropout corpus is the systematic case: the released regulators carry twenty-three circuit-kit bindings across the three open kits (ldo_005 carries no sky130 binding, while ldo_007 contributes three bindings without being counted among the seven regulators of Table III), and all twentythree pass their complete datasheets (Appendix A-B). That claim is per-entry, judged against the per-entry specification bands of Table VII, which vary deliberately across entries: the capacitor-less ldo_001 answers to looser regulation bands than ldo_005. Judged instead against the single class-level reference band defined in Table XII, 10 of the 23 bindings meet it. The two verdicts answer different questions: conformance to each entry’s own contract versus performance against a band common to the class. The benchmark reports both rather than letting the first stand in for the second. No port was mechanical, because an imported geometry encodes one technology’s assumptions. On gf180mcu the reference of ldo_007 sat below a gate-source drop of the bound device family. On sky130 a high-threshold device family drove a mirror diode of ldo_004 to the rail at the released sizing’s current density. The synthesized ldo_005 binding first resolved to the kit’s low-voltage devices and had to be re-mapped to the highvoltage family that matches its 3.3 V rail. What survives a port is the method. The detected sub-block roles of §III-B2 state which devices each rule may touch, and per-role gm /ID targets re-derive the geometry on each node through that node’s lookup tables. The tables also predict how close a port runs to its limits: ldo_009, which met a headroom bound on two kits, showed a predicted onset of regulation within 30 mV of the simulated result. Each port also adds to the entry’s record: on ldo_005 the second kit’s leakage-free models exposed a latent defect that the first kit’s models had masked (Appendix A-B), and the repaired netlist records the mechanism and the rejected repair as design notes for the next retarget.

ANALOG-DB: AN AGENT-FIRST ANALOG INTEGRATED CIRCUIT DATABASE

10

VDD Self-bias ref.

Level-shifted mirror load

Output stage

net_d

Regulation loop

VIN Mbias

M3m

M5

M6

REAnd

Buffered reference

VREF

Mp

+

Rlpf v_lpf_out

v_ref_out

A1

RZ #net1

M4

pass

net_a

net_b

M1

M2

Cc

−

−

A2

vinp

vinn

ea_out

+

#net2

R1

vout

net_f Input pair

Clpf

VOUT

v_ref_fb

VOUT

net_c vout

R2 VOUT feedback (no divider)

R3

C1

Mref

Mf

Mc

Meo

NMOS tail + sinks

VSS

VSS

(b) Error amplifier A2 (devices)

(a) Buffered-reference system

Fig. 3. The verified ldo_005_buffered_ref (Table XII), adapted from the TI TPS7A21 [48]. (a) The reference buffer A1 and an RC low-pass filter feed the error amplifier A2 , which drives the PMOS pass device; the output is compared directly against the filtered reference, with no output divider. (b) A2 , a self-biased two-stage Miller OTA with a level-shifted PMOS mirror load; the high-value tie REAnd pins the otherwise floating mirror gate rail, the one-element repair of Appendix A-B. The commercial datasheet publishes only the functional block diagram; the transistor-level realizations of A1 and A2 are authored in this work, so the entry records an adapted re-realization, not the commercial part. In silicon the rail would be pinned by a diode-connected device or a dedicated bias branch; the resistive tie is the simulation-level equivalent, and the netlist notes record it as such.

TABLE V AGENT CASE STUDY: THE L D O _005_ B U F F E R E D _ R E F DATASHEET SPECIFICATION AGAINST THE RELEASED SIZING ON EACH BOUND KIT ( TT CORNER ; 3.3 V INPUT, 1 µF OUTPUT CAPACITOR , 1 M A NOMINAL LOAD , PER TABLE VII). E VERY METRIC PASSES ; THE IHP - SG 13 G 2 PHASE MARGIN CLEARS ITS BOUND BY 1.4 ◦ .

Metric

Spec.

Output voltage (V) Quiescent current (µA) Load regulation (mV) Line regulation (mV) Dropout (mV) PSRR at 1 kHz (dB) Zout peaking (dB) Load-step undershoot (mV) Load-step settling (µs) Output noise (mVrms ) Line-step ripple (mVpp ) Loop phase margin (◦ ) Loop gain (dB) Loop unity-gain freq. (kHz)

1.50–1.70 ≤ 800 ≤ 60 ≤ 300 ≤ 400 ≥ 25 ≤ 10 ≤ 150 ≤ 30 ≤ 20 ≤ 30 ≥ 45 ≥ 50 ≥ 100

gf180mcu ihp-sg13g2 1.64 472.4 6.0 17.2 340.4 35.6 3.7 5.2 21.2 7.5 9.2 52.6 83.3 294.8

1.61 758.7 1.3 4.3 169.7 44.5 5.9 2.0 0.9 5.0 3.4 46.4 91.9 569.1

The bands target functional closure of the adapted topology on each kit, not competitive power: the ≤ 800 µA quiescent-current band sits two orders of magnitude above the 6.5 µA typical of the commercial part the topology is adapted from [48].

survived drawing and inspection. An input modulator gated the signal instead of chopping it (roughly 1.6 V/V with the clocks running against 19.3 with them static), and four device source terminals sat on floating nets, a defect invisible on the printed schematic. Debugging then hinged on locating mechanisms rather than searching over sizes: a ripple-sensing integrator ran at the chop frequency rather than twice it, a consolidation of clock phases silently inverted an impedance-boost path into positive feedback, and beneath both lay a core that is bistable without common-mode feedback. The agent closed the common-mode loop with a servo whose injection point and drive limits it chose by measurement. The study ended with composition (R4): on the open 130 nm kit, composing the sized blocks into the closed system of

§III-B5 nulled the zero-input output ripple from approximately 0.40 Vpp to below 0.1 µVpp (Table XIII), qualitatively consistent with the ripple reduction reported for the source design [8]. That residual sits at the numerical floor of a noiseless transient rather than at a measurable output level, and the composition closes the ripple loop and the common-mode loop at once, so the nulling cannot be attributed to either loop alone (Appendix A-C). All reported values are single-corner measurements; the composite’s common-mode loop is closed by an idealized servo; and on the open kits the clocked entries verify through windowed transient extraction (§V-A). A black-box baseline shows what one sizing-only search reached on the same artifact. Handed the same closed system as a flat parameter space, a Bayesian optimizer [43] produced one feasible trial in its first nineteen, reached 16 of 30 only after its bounds were narrowed to the neighborhood of a hand-seeded design point (Table VI), and had still not beaten that seed on any objective when its trial budget ran out. The binding constraint was the unregulated common mode, which no move inside the searched sizing space repaired: the optimizer could only spend its budget against it, whereas the agent diagnosed it and changed the topology. The comparison is therefore asymmetric (an autonomous sizing-only search against author-supervised sizing plus topology edits), and it locates where the failure lay without constituting a controlled comparison of two search methods on one move set. No ablation isolates which part of the representation produced that difference; what the session records show is how each part was used. The detected roles scoped each sizing rule to the devices it was meant for, and the block hierarchy let a twoloop regulator and a clocked system be debugged loop by loop. The agent identified most root causes from device operating points in the gm /ID tables before any re-size. The recorded baselines made each reported improvement a delta against a re-simulable released sizing, and the design notes on each entry record those conclusions for later sessions. Nor are the per-role sizing rules specific to the two systems reported here: the re-sized entries marked throughout the benchmark tables

ANALOG-DB: AN AGENT-FIRST ANALOG INTEGRATED CIRCUIT DATABASE

ihp-sg13g2

sky130

gf180mcu

(b)

103

(c)

160

160

140

140

120

120

DC gain (dB)

104

DC gain (dB)

Active gate area (μm2 )

(a)

11

100 80 60

10

2

10−5

10−4

Power (W)

10−3

10−2

80 60

40 10−6

100

40 105

106

107

108

Unity-gain frequency (Hz)

109

102

103

104

Active gate area (μm2 )

Fig. 4. Validated amplifier design points, colored and shaped by process kit: (a) power against active gate area, (b) DC gain against unity-gain frequency, (c) DC gain against active gate area. Every plotted point passes its evaluated datasheet at the tt corner and each kit’s default supply, under the bench conditions its record declares. Hollow markers are the 19 of 39 points recorded before the benches standardized on a uniform 10 pF load, judged under the lighter native-load benches then in force (§IV-E); filled markers are judged at the uniform load. Area is the gate-area proxy of §III-C.

TABLE VI B LACK - BOX BASELINE ON THE CLOSED INSTRUMENTATION - AMPLIFIER SYSTEM : BAYESIAN OPTIMIZATION OVER THE FLAT SIZING SPACE , 49 TRIALS ACROSS THREE NARROWED SEARCHES , JUDGED ON THE OPTIMIZER ’ S OWN BENCH ( CLOSED - LOOP SMALL - SIGNAL GAIN WITH THE CHOPPER CLOCKS HELD TRANSPARENT, 1.2 V SUPPLY; GATE AREA SUMMED OVER THE SEARCHED CORE DEVICES ONLY ).

per-cell Pareto marking therefore discriminates among real alternatives. Sizings that miss their datasheet stay in the record as starting points for a search.

Figure 4 plots every validated design point (§III-B1) on the amplifier scoreboard, whereas the tables of Appendix A-A report only the single released sizing per entry. Of the 327 recorded amplifier design points at the archived revision, 39 are Search space Dim. Feasible trials validated (the behavioral amp_028 is excluded). The validated Devices + bias inputs, bounds 0.3×–3× 18 0 of 4 points span more than four decades of power (0.6 µW to Devices only, bounds 0.3×–3× 14 1 of 15 Devices only, bounds 0.6×–1.7× 14 16 of 30 7.7 mW), two and a half decades of active gate area, and DC gains of 40 to 160 dB at unity-gain frequencies from A trial is feasible when it satisfies every constraint of the optimizer’s problem; the best-scoring trial need not be feasible. The hand seed (the 33 kHz to 528 MHz, and the three open kits interleave across released sizing defaults, never evaluated as an optimizer trial) dominates the best trial on all three objectives: gain 25.713 vs. 25.611 dB, power 263.4 vs. all three panels rather than stratifying into per-kit bands. Two 283.9 µW, searched-device gate area 96.8 vs. 127.2 µm2 . The system row of caveats apply. First, each point is judged under the bench Table XIII is a different measurement of a later sizing: clocked conditions in force when it was recorded: the amplifier benches windowed-transient gain at the 5 kHz chop, gate area over all 75 devices. are standardized to a uniform 10 pF load at the archived revision, but the scoreboard retains earlier points recorded of Appendix A were closed by constrained re-optimization against lighter native-load benches, and the widest unity-gain frequencies, including the 528 MHz endpoint (a legacy-bench combined with those same rules. No like-for-like simulator-cost comparison is reported. Black- record of amp_018), are among those; the figure draws these box re-sizing consumed hundreds of recorded evaluations per 19 legacy-bench points hollow so the two populations stay circuit and kit, while the agent loop closed each regulator distinguishable. Second, the highest DC gains are nominal binding within four recorded full-suite runs; but the agent’s schematic measurements of re-optimized gf180mcu sizings, single-bench diagnostic probes were not logged and the and the mechanism behind them is the re-optimizer driving supervision itself carries no cost record, so the two recorded channel lengths to the geometry bound: gain per stage scales costs count different things, and a per-evaluation table would as (gm /ID )/λ, and λ falls with L, so on a 180 nm process a constrained search trades area for gain and phase margin. understate the agent side. These readings are physically reachable rather than erroneous, but they cost area. Appendix A-A marks the most extreme of E. Scoreboard Coverage and Optimization Support (RQ5) them against an absolute area threshold and names what that RQ5 tests the optimization support the scoreboard of §III-C threshold leaves unmarked, since the same mechanism operates provides. At the archived revision the record holds 457 design below it. points, and 127 of the 159 populated circuit-kit cells (one Figure 5 gives the regulator view, plotting the 34 validated scoreboard cell per circuit and kit) carry two or more; the of the 71 recorded design points over power, area, supply

ANALOG-DB: AN AGENT-FIRST ANALOG INTEGRATED CIRCUIT DATABASE

ihp-sg13g2

(a)

12

sky130

gf180mcu

(b)

(c)

103

102

60

Dropout voltage (V)

PSRR at VDD (dB)

Active gate area (μm2 )

70

50 40 30 20 10

10−4

Power (W)

10−3

10−4

Power (W)

10−3

10−1

10−2

10−3

10−2

10−1

Load regulation (V)

100

Fig. 5. Validated regulator design points: (a) power against active gate area, (b) power-supply rejection at VDD against power, (c) dropout voltage against load regulation. Every plotted point passes its evaluated datasheet at the tt corner, under the LDO class benches at each entry’s datasheet operating conditions (Appendix A-B). Filled markers are the 10 of 34 points that also sit inside the class-level reference band of Table XII; hollow markers pass their own datasheet but fall outside it, or record too few band metrics to judge: all twenty-three baselines are judged, while the eleven unjudged points are alternative sizings predating the loop-break marker (Appendix A-B).

rejection, dropout, and load regulation. The panels project onto regulation metrics because only one regulator’s datasheet declares a loop-gain bound at this revision, though the loop is now measured on every binding. Both figures are generated by script from the released catalog and scoreboard artifacts, so any reader with the archived revision can regenerate them.

V. D ISCUSSION Taken together, the five research questions support one conclusion: the obstacles to sharing analog designs are representational rather than fundamental. Once a design is distributed as one schema-governed object containing its topology, parameter space, contract, and bindings, then reproducibility, portability, and machine actionability are carried by the representation rather than by each author’s release practice. The case studies indicate what changes as a consequence: design knowledge that today survives only as a table in a paper becomes an artifact a later designer or agent can re-run, re-size, and extend, and each such use can leave a new recorded design point on the entry it drew from. The limitations below bound where this claim holds at the current release. One methodological finding deserves prominence beyond its table footnote: a loop phase margin certifies only the loop it measures. On gf180mcu, 021_yan_az sustains a 1.84 Vpp self-starting oscillation with the input held at DC while its outer-loop margin reads +69◦ . The oscillator is internal to the cell, where neither open-loop bench can see it. The corpus therefore treats a zero-input transient as the deciding stability check, and this case is why: a benchmark that certified stability by loop margin alone would have published an oscillator as a passing entry.

A. Limitations Structural annotation is bounded by the template library at the archived revision. The matcher assigns a role to 51% of the corpus’s devices (§IV-A) because structures outside that devicelevel library contribute nothing: no common-mode-feedback template exists at this revision (§III-B2), and a common-mode loop composed from a released entry is annotated only where its own devices match a device-level template. On amp_029 and its CMFB-closed composite amp_030 (§III-B5) this leaves 38% and 25% of devices with an assigned role, against 51% across the corpus. Growing the library and re-running detection is the first direction of §V-B. The corpus is amplifier-weighted. Amplifiers and OTAs account for 33 of the 68 circuits, while the data-converter, sampler, and trim classes hold one entry each (Table III), so the representation’s generality beyond amplifier-like blocks is less exercised than its depth on amplifiers. The agent evidence is a pair of case studies, not a controlled experiment. Both sessions were author-supervised runs of a single coding agent and model, the supervision record is limited to per-session engineering reports that are not themselves part of the release, and the comparison arm that would isolate the contribution of the structural artifacts—an agent denied those artifacts—has not been run. The recorded simulator costs of the two disciplines count different things (§IV-D), so no cost comparison is tabulated. The optimizer baseline is additionally asymmetric, sizing-only against sizing plus topology edits (§IV-D). The studies establish feasibility—that an agent working only from the released artifacts can reach datasheet compliance—and attribute nothing causally to any individual artifact. Device mismatch is not modeled. Every reported figure comes from a nominal schematic with perfectly matched

ANALOG-DB: AN AGENT-FIRST ANALOG INTEGRATED CIRCUIT DATABASE

13

devices, so the rejection, offset, and residual-ripple values that mismatch sets in silicon are systematic CMRR/PSRR (mismatch excluded) upper bounds (§III-B4), and readings at the simulator’s resolution floor are reported as bounds rather than values (Appendix A-A). Recorded results are single-corner: every design point at the archived revision was evaluated at the typical corner, and the released gm /ID tables are characterized there. Multi-corner PVT evaluation and optimization remain future work. Verification depth for clocked circuits is limited by the simulator. Small-signal analysis is invalid for a chopper or switched-capacitor circuit because it freezes the switches in one state, and the open-source simulator (§III-C) offers no periodic steady-state alternative. On the open kits these entries fall back to windowed transient analyses, leaving band-shape metrics as specification targets rather than measured values (Appendix A-C), and no released entry yet carries a periodic steady-state characterization. The clocked circuits are therefore the least uniformly verified part of the corpus. Finally, all verification is pre-layout. No entry carries a layout or extracted parasitics, the recorded area is the acknowledged gate-area proxy of §III-C, and no released result has yet been correlated against silicon.

cores into a closed-loop system, with an idealized commonmode servo. In doing so it located four defects introduced during hand entry, and a missing common-mode feedback loop that the sizing-only baseline did not repair. analog-db is released as a versioned, open corpus of 68 verifiable circuits across sixteen classes. Every entry ships with its testbenches, and 65 of the 68 carry recorded design points, so that every reported result can be re-run and extended.

B. Future Work Three directions follow. The first is detection coverage: adding a common-mode-feedback family to the sub-block template library (Table II) and growing the library further, starting with the pending pseudo-resistor variants, then rerunning detection, would raise the structural coverage reported in §IV-A. The second is hierarchy above the sub-block level: an LLM annotation layer, cross-checked against the deterministic matcher beneath it, could identify and verify abstractions that subgraph matching cannot name, such as gain stages and signal chains, and record them as queryable taxonomy metadata alongside the structural roles. The third is breadth: new entries in the thin classes, notably data converters, and advanced low-power OTA topologies such as subthreshold and currentreuse designs, each entering through the same schema and verification harness as the existing corpus. Beyond these, the protocol wrapper of §III-B6 remains future work: it would simplify access over the same files rather than extend them. VI. C ONCLUSION This paper presented analog-db, a database built on a foundryneutral representation that captures each design as a topology, a set of testbenches, and a machine-readable datasheet under one schema. Entries annotate functional sub-blocks with parameters that carry their matching constraints, and verified blocks compose into larger systems. A file contract exposes them to AI agents, while generated schematic views keep them readable to designers. Derived decks regenerate byte-identically, every entry carries a graded verification status, and the audited baselines reproduce bit for bit at the archived revision. Working only from the released artifacts, a supervised coding agent carried an LDO to full datasheet compliance on two kits. It assembled a published chopper instrumentation amplifier from its op-amp

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A PPENDIX A B ENCHMARK R ESULTS This appendix reports the recorded design points behind the scoreboard claims of §III-C, one subsection per benchmarked class. The landscape Tables IX–XIII are gathered at the end of the paper. All tabulated values are re-simulated from the released database at its archived revision, except where a table footnote records otherwise; none are transcribed from the source publications.

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TABLE VII P ER - ENTRY DATASHEET SPECIFICATION BANDS AND OPERATING CONDITIONS FOR THE LDO BENCHMARK (TABLE XII, WHOSE ROW ORDER AND ACCESSION NUMBERS THESE SHARE ), READ MECHANICALLY FROM EACH ENTRY ’ S RELEASED DATASHEET AND BENCH BINDINGS . T HE LAST HEADER ROW GIVES EACH COLUMN ’ S BOUND DIRECTION . Conditions

Specification band

Circuit

Vin (V)

Cout

Iload (mA)

Load step (mA)

Load range (mA)

Vout (V) window

Dropout (mV) max

Load reg. (mV) max

Line reg. (mV) max

PSRR (dB) min

Zout (dB) max

Under. (mV) max

Iq (µA) max

001 002 003 004 005 007 008 009

1.8 2 2 1.8 3.3 1.8 1.8 1.8

50 pF 50 pF 50 pF 1 µF 1 µF 1 µF 1 µF 1 µF

5 10 10 1 1 1 1 1

5→55 0.01→10 0.01→10 1→10 1→10 1→10 1→10 1→10

0–55 0–10 0–10 0–10 0–10 0–10 0–10 0–10

1.50–1.70 1.70–1.90 1.70–1.95 1.25–1.35 1.50–1.70 1.16–1.24 1.10–1.30 0.85–0.95

300 300 300 300 400 300 500 500

800 20 150 150 60 20 100 100

300 50 50 30 300 20 50 50

5 40 20 20 25 30 20 20

35 45 25 15 10 8 20 20

1500 1000 1200 150 150 100 300 300

100 500 500 250 800 250 500 100

Bands are authored per entry, so “passes its datasheet” is a per-entry claim: the relaxed 001 bands (a capacitor-less regulator) and the tight 005 bands are both visible rather than hidden behind one verdict. The dropout bench of 007 at 10 mA against a 1 mA nominal load runs heavier than nominal; every other entry’s dropout is judged at its nominal load.

Transient simulation resolved the ambiguity: every entry the corrected reference drives negative sustains a limit cycle that Table IX reports the power, performance, and area of every self-starts with the input held at DC, while every entry it leaves amplifier and OTA with an IHP 130 nm (ihp-sg13g2) alone settles. The corrected benches agree with the independent binding at its released sizing. Tables X and XI give the loop-gain bench on 13 of 14 comparable entries, where they same view for the GF180MCU and SKY130 bindings. Entries had differed by up to 89◦ . With the corrected reference in force, marked § do not retain their originally imported sizing. Stability one of the 87 published amplifier circuit-kit baselines carrying verification found the imported points electrically dead (no a phase-margin cell (030_miller_cmfb_composite on device biased into a working operating region), unstable, or ihp-sg13g2) sits below the 45◦ floor, at 33.3◦ . The floor itself marginally stable, and they were re-sized by constrained reis a permissive bound (design practice and vendor datasheets optimization combined with per-role gm /ID sizing. The table more commonly ask for 60◦ ), so clearing it certifies stability footnotes record the affected entries and the failure each of the recorded point, not competitive phase margin. Two exhibited. Throughout these tables, a circuit’s per-kit rows are gf180mcu entries are withheld from the tables entirely, and independently sized realizations of one topology, not one design named in their footnote, because no sizing was found for measured three times, so power, gain, and area may differ them that is both stable and in specification: 011_peng_iac, widely across kits (025_hsu_classab_ota spans 13.1 µW whose only stabilizing sizing costs 37 dB of PSRR, and on sky130 to 1752 µW on gf180mcu). Where a re-optimizer 021_yan_az, which self-oscillates at 1.84 Vpp held at DC reached stability by pushing geometry to its bounds, the row is and keeps oscillating with the outer loop AC-opened, even as its marked as an optimizer artifact rather than a defensible design outer-loop margin reads +69◦ (§V). Both circuits remain in the (footnote of Table X). database with their other kits and their recorded measurements; That verification also uncovered a defect in the measurement what is withheld is the claim of a design point, while the itself rather than in the circuits, one invisible to inspection data remain. The uniform 10 pF load these tables share is a of the recorded values. Both open-loop benches referenced deliberate departure from each source’s own operating point, phase to the first swept point, which is correct only while made for cross-cell comparability: the AnalogGym shared that point lies below the dominant pole; at a 163.6 dB amplifier testbench, for example, loads all seventeen of its plateau the dominant pole fp = UGF/A0 sits in the tens of amplifier netlists with 500 pF at a 1.8 V supply, so re-simulating millihertz, under the benches’ 0.1 Hz reference. Measured on those netlists at 10 pF at each kit’s own supply moves multistage 006_leung_dfcfc1 on gf180mcu at the sizing then under nested-Miller compensation designs 50× from the load they verification, the raw unwrapped phase at 0.1 Hz sat 78.6◦ below were compensated for, and partly explains why many imported its 1 µHz value, and the self-reference subtracted that accrued sizings failed stability verification before re-sizing. Table VIII lag from every point including the crossover: the bench reported lists every cell evaluated 10× or more from its as-published +72.7◦ where the true margin was −5.9◦ , and read 150.0 dB load; those rows are not comparable to the source publication’s off the 163.6 dB plateau. (The row Table X tabulates for this numbers, and the native values are retained so a reader can entry is the later re-sized design point, at 1.32 MHz.) The repair re-run any entry at its published operating point. The chopper keeps the unwrapped phase and its start-of-sweep reference rows record one architectural finding: the chopper OTA core and moves the sweep start below the dominant pole (10−4 Hz (026) carries no common-mode feedback and its systematic on the affected high-gain cells), where lowering it further does CMRR/PSRR (mismatch excluded) is correspondingly poor, not change the reported margin. Six entries were affected, while its CMFB-closed variant (034) recovers more than 40 dB all of them high-gain multi-stage cells on gf180mcu, and the of both on ihp-sg13g2 for less than 1 dB of differential gain error is not a constant offset: it tracks each amplifier’s own fp . A. Amplifier Benchmark

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10 Hz value over 10 Hz–10 MHz. That is a proxy rather than a damping measurement, and it fails in two opposite directions. Referenced to its own 10 Hz value, the reading tracks how far VALUES ARE KEPT SO EACH RESULT CAN ALSO BE READ AGAINST ITS the regulation loop has already rolled off by the frequency SOURCE PUBLICATION ’ S OPERATING POINT. of the peak, which is a statement about loop gain rather than about damping. And an entry whose output capacitor holds Circuit Native CL |Zout | under its low-frequency value across the whole sweep amp_021 15 nF reads 0 dB whether its loop is well damped or barely closed. amp_013 1.5 nF The corpus splits on exactly that line: 001, 002 and 003 amp_017 560 pF are capacitor-less entries carrying 50 pF, and all nine of their amp_015 500 pF bindings fail the 10 dB sub-band, which is nine of the eleven amp_016 500 pF amp_011 150 pF failures; the remaining entries carry 1 µF, and seven of the amp_012 150 pF twenty-three bindings sit on the 0.0 dB floor exactly. amp_002 100 pF Binding ac_loopgain across the class was a queued amp_005 100 pF database update; it was applied in analog-db v1.1.2, so amp_006 100 pF pm_loop_deg is now recorded on all twenty-three baselines amp_007 100 pF amp_010 100 pF and the band of Table XII is judged on it, against the 45◦ amp_014 100 pF bound 005 already carries in its own datasheet (Table V). On amp_022 500 fF the same pin the output-impedance proxy puts 3 of 23 within amp_023 500 fF the class band and the phase-margin band puts 10 of 23, so amp_001 50 fF the shift is a change of measurement, not a change of corpus. amp_018 50 fF amp_025 50 fF The two disagree in the direction the construction predicts. amp_026 50 fF The nine capacitor-less bindings the proxy penalized hardest amp_027 50 fF measure 89.5◦ to 136.0◦ of phase margin, among the best amp_029 50 fF damped in the corpus, while the one binding that fails the amp_030 50 fF phase-margin sub-band, 008 on gf180mcu at 35.3◦ , ranked amp_031 50 fF only eleventh of twenty-three on the proxy at 12.5 dB: flagged, but below all nine of them. The failures now concentrate in Iq rather than in a stability reading. The same sweep yields (footnote of Table IX). the sensitivity-function peak max |Zout,cl |/|Zout,ol |, recorded as ms_peak_db and reported but not judged, since no entry B. LDO Benchmark carries an authored bound for it. The top panel of Table XII reports the low-dropout regulators Eight entries appear against the seven counted in Table III with an ihp-sg13g2 binding, measured by the LDO class because the benchmark includes 007, which the coverage benches against the per-entry specification bands and operating table excludes as incomplete. Seven of the eight entries conditions of Table VII: load and line regulation, dropout, were re-sized (marked ¶) after the imported sizings exhibited power-supply rejection at 1 kHz, the loop phase margin (with under-damped or collapsing load-step responses (001–003), the limits set out below), and a load-step transient at each a 559 mV dropout (007), a dropout bench invalidated by outentry’s own step. The class benches fix the operational defini- of-window regulation (004), and a −17 dB PSRR reading that tions: dropout is the smallest Vin − Vout at which the output traced to a failed DC solve rather than a real supply path is simultaneously within 50 mV of its target and decoupled (009). Re-sizing followed the per-role gm /ID loop of §IV-D, from the input (|dVout /dVin | ≤ 0.1), so a pass device that is starting from each circuit’s detected sub-blocks (current mirrors, off and merely follows the input cannot report a near-zero differential pairs, tail sources). dropout; load and line regulation are each the total output The same procedure was then applied to the gf180mcu and excursion in volts (no slope normalization) across the full DC sky130 panels of Table XII, where the imported sizings failed load and supply sweeps; the loop phase margin is taken by the in technology-specific ways; the fixes from the first kit did not ac_loopgain bench under Middlebrook voltage injection at carry over mechanically. The error amplifier of 007 latched a 0 V break marker placed inside the device under test, so it off from power-up on gf180mcu because its 0.6 V reference measures the regulation loop directly rather than inferring it sits below one gate-source drop of that kit’s 3.3 V device from the closed-loop output impedance; load-step undershoot family, so the earlier 104 dB PSRR figure had measured supply is measured against the post-step settled output rather than the coupling into a disconnected node. 009 met the same headroom pre-step value; output noise is the output-referred rms integrated bound on both kits, with the predicted onset of regulation over 10 Hz–10 MHz; and line-step ripple is the peak-to-peak matching the simulated result to within 30 mV. The bufferedoutput deviation over a window spanning both supply edges, reference regulator 005 [48] (Fig. 3) exposed a latent netlist so it includes the DC line-regulation shift between the two defect: the gate rail of its level-shifted mirror load was defined rails as well as the transient excursions. only by device leakage, which gf180mcu’s BSIM4 models Through v1.1.1 this band judged stability on closed-loop supply and IHP’s leakage-free PSP models do not, leaving a output-impedance peaking instead: the rise of |Zout | above its stable but incorrect equilibrium that railed every DC sweep. TABLE VIII C ELLS EVALUATED 10× OR MORE FROM THEIR AS - PUBLISHED LOAD UNDER THE UNIFORM 10 P F CONDITION . T HE UNIFORM LOAD IS WHAT MAKES THE CROSS - CORPUS COMPARISON A COMPARISON ; THE NATIVE

ANALOG-DB: AN AGENT-FIRST ANALOG INTEGRATED CIRCUIT DATABASE

17

A one-element repair—a resistive tie from the mirror drain (spicexplorer/<kind>@1) validated at Tier 0, and every to the gate rail (50 kΩ on gf180mcu, 500 kΩ on ihp-sg13g2) excerpt below is taken verbatim from the released database that carries no DC current by construction—together with a (elisions marked ...). Throughout, the listings mark the compensation retune, made the circuit datasheet-compliant on authored/generated split of §III-B1 in comment. both kits. The 340 mV dropout on gf180mcu falls inside the 400 mV specification that sizing alone had been unable to reach A. Expressing Parametrization on the defective netlist. The root-cause record for each repair Parametrization splits the two layers of §III-B3 across two is stored with the entry, as design notes in its released netlist. artifacts. The process-neutral abstract/params.yaml carries the generated device-to-symbol map and the authored C. Instrumentation-Amplifier / Bio-AFE Benchmark ties beneath it, where groups declare structural matching and The six instrumentation-amplifier entries derive from two ratios freeze multiplier relationships. published designs: the chopper capacitively coupled instrumen- schema: spicexplorer/params@1 # GENERATED from abstract/ tation amplifier with ripple-reduction loop of Fan et al. [8] and devices: topology.cgraph.json the Hsu biomedical analog front-end chain [46]. Table XIII CC: {Value: x_dut_cc_value} reports their figures and per-entry status at the released sizing XM0: {l: x_dut_xm0_l, m: x_dut_xm0_m, w: x_dut_xm0_w} on ihp-sg13g2. Chopper entries are characterized with ... # one row per device (11 their clocks running, through transient analyses at the 5 kHz devices) system chop frequency, each measured over a window placed groups: # AUTHORED default tying, human-reviewed after that entry’s own settling transient, since the small-signal name: input_pair benches that freeze the switches are invalid for the class - kind: matched_pair (§V-A). The input impedance is derived from the average members: [XM0, XM1] tie: [w, l, m] commutated input current, and the band-shape metrics remain description: PMOS differential input pair - fullspecification targets bound only where a continuous-time geometry match bench is valid. The composite ia_004 exercises the closure ... # frozen gains survive as property of §III-B5 on a complete system, composing the ratios: ratios, not free knobs bare amplifier (ia_002) with the switched-capacitor ripple - {param: m, ref: XM6, of: XM7, ratio: 17/3, loop and an ideal common-mode servo on the core’s shared description: Stage-2 current-source gain (legacy m=17 vs 3), frozen.} current-source gate. The loop is clocked at twice the chop rate so its two-phase network completes one sample-and- Listing 1. amp_022: abstract/params.yaml: generated transfer cycle in each half-period of the demodulated waveform; device→symbol map, authored tying. The per-PDK pdk/<pdk>/sizing.yaml binding then both half-periods contribute charge—the factor of two in the loop’s measured 2(Cs /Cint )fchop transfer. Because the supplies the per-technology defaults and bands, and freeze: release simulates matched devices, the up-modulated offset true is how a parameter is withheld from the search without ripple this loop removes in silicon is absent by construction leaving the record. here; the ∼0.40 Vpp zero-input ripple of the loop-less core is schema: spicexplorer/sizing@1 recorded as chopping ripple, growing as 1/fchop , compounded pdk: ihp-sg13g2 variables: by the unregulated output common mode, which is bistable - {name: x_dut_xm0_w, description: "PMOS input pair width per finger under the running clocks (a ∼0.7 ms relaxation oscillation (XM0; XM1 tied, m=5)", default: 8u, min: 0.18u, through the capacitive network). Composing in the loop and max: 50u, unit: m} the servo together nulls it below 0.1 µVpp , the numerical floor - {name: x_dut_cc_value, description: "Miller compensation cap (F)", of the noiseless transient; the composition closes both loops at default: 2e-12, min: 2e-13, max: 1e-11, unit: F} once, so the nulling is attributed to the pair, and the variant - {name: x_dut_xm0_m, description: "Input pair that would separate them (006) binds only its DC operating fingers (frozen; XM1 tied)", default: 5, min: 1, max: 16, freeze: true, point at this revision. The supporting front-end blocks are is_integer: true} held as separate entries: the amplifier core OTAs appear in ... Table IX (026/027/031), and the Hsu switched-capacitor 2. amp_022: pdk/ihp-sg13g2/sizing.yaml: per-PDK common-mode feedback block reaches validated status (§III-C) Listing defaults, bounds, freezes. standalone at its 1 kHz system clock. A simulated design point records the result: the scoreboard A PPENDIX B D OMAIN -S PECIFIC L ANGUAGE This appendix presents the concrete syntax of the representation and the design decisions behind its schemas, using one circuit from the corpus as a running example: the twostage Miller OTA amp_022_fer_two_stage, with the composite amp_030_miller_cmfb_composite illustrating hierarchy. Every artifact conforms to a versioned schema

stores the same symbols with concrete values, keyed by a design_id that hashes {circuit, PDK, sizing}. { "design_id": "9c0de4bdfb", "circuit": "amp_008_leung_nmcf", "pdk": "ihpsg13g2", "parameters": { "sizing": { "CAPACITOR_0": "5p", "CURRENT_0_BIAS": 1.2393e -05, "x_dut_xm7_w": 5.8248e-07, ... } }, "metrics": { "tt": { "pm_deg": {"value": 61.069, " spec": "pass"},

ANALOG-DB: AN AGENT-FIRST ANALOG INTEGRATED CIRCUIT DATABASE

... } } } Listing 3. A recorded design (scoreboard/ihp-sg13g2/<design_id>.json, excerpt).

point

B. Expressing Metrics and Testbenches The class registry (_shared/classes/amplifier/) owns the canonical metric vocabulary and the testbench templates; a circuit’s analyses/<id>.yaml instantiates one template at stated operating conditions. This keeps the corpus measurable with one vocabulary (the same pm_deg means the same bench everywhere) while each circuit states only its numbers. schema: spicexplorer/analysis@1 id: ac_open_loop template: ac_open_loop_biaswrap_ibias # classowned .spice template description: "Bias-wrapped open-loop AC gain/phase." params: {VDD: 1.5, VCM: 0.6, IBIAS: 20u, CL: 500f, FSTART: 1, FSTOP: 1G, PPD: 50} flags: [bias_wrap] # 1T-L / 1T-C wrap: DCclosed, AC-open loop produces: [dc_gain_db, ugf_hz, pm_deg] Listing 4. amp_022: analyses/ac_open_loop.yaml: an analysis instantiates a template.

The datasheet.yaml declares, per canonical metric, where it comes from (analysis + extract) and what passing means (spec); the verification harness and the scoreboard both judge against this one artifact. schema: spicexplorer/datasheet@1 default_conditions: supply: {unit: V, typical: 1.5} cload: {unit: fF, typical: 500} metrics: ... pm_deg: analysis: ac_open_loop extract: {meas: pm} spec: {min: 60.0, max: 90, unit: deg} ... Listing 5. amp_022: datasheet.yaml (excerpt): metric = analysis + extraction + spec.

C. Expressing PDKs and Simulators PDK knowledge lives in one registry per technology (_shared/pdk/<pdk>.yaml); corner libraries stay out of the repository and are referenced by file name and section, so the database clones and verifies PDK-free through the kit-free tiers of §III-C, while the simulation tiers gate on PDK presence. The sim_engine marker selects the simulator backend; every released PDK is simulated with ngspice. pdk: ihp-sg13g2 sim_engine: ngspice # in-library router marker (open lane) supply: {default: 1.5, unit: V} devices: nmos: {lv: sg13_lv_nmos, hv: sg13_hv_nmos} pmos: {lv: sg13_lv_pmos, hv: sg13_hv_pmos} corners: lib_file: cornerMOSlv.lib sections: [mos_tt, mos_ss, mos_ff, mos_sf, mos_fs] geometry: {min_l: 0.13u, min_w: 0.18u, max_l: 10u, max_w: 10u} ... Listing 6. _shared/pdk/ihp-sg13g2.yaml (excerpt): engine marker, device classes, corners, geometry rules.

18

Each circuit binding then maps its generic device kinds onto that registry and names its corner selections. Retargeting a circuit to an additional process kit requires only these files plus sizing.yaml: # pdk/ihp-sg13g2/devices.map.yaml devices: nmos: {model: sg13_lv_nmos} pmos: {model: sg13_lv_pmos} # pdk/ihp-sg13g2/corners.yaml corners: tt: [{lib_file: cornerMOSlv.lib, section: mos_tt}] ... default_corner: tt Listing 7. amp_022: per-circuit PDK binding: generic→kit device map and corner selections.

D. Expressing Hierarchy and Sub-blocks A composite circuit is an authored manifest (spicexplorer/composition@1) over existing database entries: each instance names a block and pins the exact revision of its topology (a content hash the compose validator checks), wires its ports, and may tap internal nets, omit block-local bias elements, or override a block’s parameters. These are the composite-level adjustments of §III-B5 in concrete syntax; the flattened netlist and sizing binding the generation step emits are themselves generated, and checked by T1 for byte-identical regeneration. schema: spicexplorer/composition@1 of: amp_030_miller_cmfb_composite instances: - name: core block: amp_029_two_stage_miller_comp pin: 67c6e24e4137 # pinned topology revision (content hash) ports: {vinp: vinp, vinn: vinn, voutp: voutp, voutn: voutn, vdd: vdd, vss: vss} taps: {vbl: vbl_ctl} # expose an internal bias net omit: [Vbl] # composite owns this bias now - name: servo block: cmfb_001_ideal_rsense_servo pin: 9c8861186398 ports: {vinp: voutp, vinn: voutn, vcmfb: vcmfb_raw , vref: vref_cm, vdd: vdd, vss: vss} override: {rout_val: 10k} # gain-1 correction ( range-referencing) nets: # composite-level glue - "Vrefcm vref_cm vss dc {vcm_ref}" - "Vbl0 vbl_ctl vcmfb_raw dc {vbl0}" sizing: # composite-owned knobs ... Listing 8. amp_030_miller_cmfb_composite: composition.yaml (condensed): CMFB closure of amp_029 by a behavioral servo block.

A PPENDIX C A RTIFACT AVAILABILITY analog-db is released publicly as the analog-db/ component of the spicexplorer-release repository, https: //github.com/MacAnalog/spicexplorer-release. Every result reported here comes from release v1.1.2 of that repository, the archived revision referred to throughout.

Circuit 001_5t 002_alfio_raffc†§ 003_fan_smc† 004_folded_cascode 005_hoilee_affc†§ 006_leung_dfcfc1†§ 007_leung_dfcfc2† 008_leung_nmcf†§ 009_leung_nmcnr† 010_peng_acbc†§ 011_peng_iac†§ 012_peng_tcfc†§ 013_qu2017_azc† 014_ramos_pfc† 015_sau_cfcc† 016_song_dacfc† 018_telescopic_cascode§ 019_ti_ldo_error§ 021_yan_az†§ 022_fer_two_stage 023_fer_fd2s 024_smcnr† 025_hsu_classab_ota§ 026_fan_chopper_ota 027_fan_rrl_ota 030_miller_cmfb_composite 031_srmc_core_cmfb [46] 017_tan_clia† 032_ti_ldo_error_selfbias 033_ti_ldo_ref_selfbias 034_fan_chopper_cmfb 035_fan_chopper_cmfb_dual

Stages Comp. 1 3 3 1 3 3 3 3 3 3 3 3 3 3 3 3 1 2 3 2 2 2 2 2 1 2 2 3 2 2 2 2

none RAFFC SMC none AFFC DFCFC1 DFCFC2 NMCF NMCNR ACBC IAC TCFC AZC PFC CFCC DACFC none none AZ miller miller_nulling miller_nulling miller-rz miller — miller miller-rz CLIA Rz+Cc∗ Rz+Cc∗ miller miller

Gain (dB) UGF (MHz) PM (◦ ) CMRR (dB) PSRR (dB) Power (µW) Gate area (µm2 ) 32.5 103.9 86.0 44.1 97.5 93.8 91.3 89.4 95.6 84.4 109.6 102.3 80.1 102.1 87.4 72.1 52.2 50.0 129.4 51.5 65.9 69.4 35.8 59.7 46.6 50.1 54.7 43.8 50.0 56.1 58.9 60.3

1.21 2.41 6.64 2.03 3.50 1.92 2.78 3.16 1.44 1.31 1.76 2.01 3.78 1.94 7.06 1.91 0.30 11.63 2.19 19.16 25.25 0.15 49.14 6.16 3.61 13.76 5.84 1.95 18.28 29.17 6.11 6.20

86.9 75.1 85.8 74.8 103.8 75.4 78.4 62.7 89.3 86.4 82.3 71.4 88.7 81.5 82.5 106.4 88.9 74.3 92.0 63.4 73.6 58.2 53.5 59.4 89.9 33.3 71.3 59.9 69.6 80.3 58.2 62.9

49.5 82.8 67.8 72.9 74.9 87.4 90.6 86.6 91.0 86.8 133.6 100.9 90.2 102.6 77.6 75.1 96.5 54.8 43.1 64.3 95.8 96.4 98.9 10.4¶ 52.8 80.6 145.1 49.8 56.5 50.7 53.8 110.9

32.7 83.4 54.4 39.6 80.5 57.7 63.5 65.6 63.2 49.8 64.5 63.9 76.8 61.8 56.5 39.7 52.7 51.2 51.9 76.4 100.2 105.5 127.7 -2.4¶ 63.4 50.2 114.6 56.1 57.0 68.7 41.0 90.4

59.3 605.2 1589.4 233.0 342.0 692.3 448.7 315.2 117.6 648.5 37.1 122.4 87.4 754.5 295.2 252.6 11.4 10505.3 121.0 369.0 824.6 2.0 208.3 268.9 77.1 218.0 116.2 123.3 195.2 236.9 272.2 328.0

vn,in

BW vn,in

THD

348 30.9 33.2 0.109 1892 40.9 66.6 0.012 412 189.0 219.5 0.020 3556 42.0 67.7 0.769 2200 39.7 76.3 0.026 12803 17.7 24.4 0.001 440 52.9 80.6 0.001 646 65.1 86.4 0.003 272 106.2 115.7 0.001 1549 83.2 87.2 0.003 1273 89.2 127.9 – 1691 93.8 122.9 – 204 291.3 383.0 – 2583 20.6 27.2 <0.001 4351 42.3 82.4 1.069 472 395.4 475.5 0.165 97 125.3 113.2 0.017 437 20.3 31.2 0.020 1258 72.4 80.6 2.094 176 44.4 82.2 0.022 92 79.4 116.3 0.001 332 280.6 71.4 0.015 123 1130.9 6613.9 6.589 141 76.1 95.8 <0.001 83 56.3 65.2 0.006 58 42.2 73.8 0.002 14 59.4 72.7 – 11128 56.1 74.5 0.380 1443 40.7 73.6 0.075 37 52.3 82.1 0.008 148 76.1 – – 156 76.2 – –

ANALOG-DB: AN AGENT-FIRST ANALOG INTEGRATED CIRCUIT DATABASE

TABLE IX A MPLIFIER /OTA BENCHMARK IN IHP 130 NM ( I H P - S G 13 G 2), AT THE RELEASED SIZING OF EACH ENTRY. A LL VALUES ARE RE - SIMULATED UNDER UNIFORM CONDITIONS (CL =10 P F, UNITY- GAIN BUFFER ; NOISE 1 H Z –1 MH Z ; THD PER THE FOOTNOTE ).

— and – mark a cell with no value: not applicable, not recorded in this configuration, or a recorded bench failure. † AnalogGym-sourced, ported from its native sky130 testbenches. § Re-sized after failing stability verification (imported phase margin below 45◦ ); re-optimization constrained it to 60–90◦ . 002 was conditionally unstable and was re-sized to a 5.7 dB gain margin.

19

∗ Abbreviated compensation scheme: Rz+Cc = “Rz + Cc from the first-stage node to the output”. Fully-differential rows report the systematic CMRR/PSRR (mismatch excluded), measured on the common-mode path with the differential gain folded in. ¶ Chopper core characterized with its output chopper held static; chopping leaves the CM path unchanged, and with no CMFB the rejection is CMFB-limited. Adding one (034_fan_chopper_cmfb) improves both CM-path columns by 43.4 dB on ihp-sg13g2 for 0.8 dB of differential gain. PM is the stb loop-probe reading (pm_loop_deg) where that bench’s unity crossing agrees with the AC sweep to within 20 %, and the AC-sweep reading (pm_deg) otherwise; either is folded into (−180◦ , 180◦ ]. Here every tabulated PM cell is the stb loop-probe reading. Both readings are carried per design point in the released scoreboard. Both noise columns are µVrms ; THD is % (single-tone, 0.1 V, or 0.05 V where the swing would clip, at a per-cell frequency set from its UGF, harmonics 2–5). Gate area is the summed gate area of the sized devices only; capacitor and resistor area is excluded (§III-C). 017 is tabulated for information but excluded from the counted corpus; the counted 028 (behavioral) and 029 (no recorded baseline) are not tabulated. The ∼10 mW of 019_ti_ldo_error is design intent: the source design’s 1 mA reference is mirrored at near-unity ratio into the tail and output legs. BW each cell’s own 1 Hz–UGF band; the uniform band overstates a slow cell (up to 7.8×) and understates a fast one (down to 0.17×). vn,in integrates the uniform 1 Hz–1 MHz comparison band, vn,in

Circuit 001_5t§ 002_alfio_raffc†§ 003_fan_smc†§ 004_folded_cascode§ 005_hoilee_affc†§ 006_leung_dfcfc1†§ 007_leung_dfcfc2†§ 008_leung_nmcf†§ 009_leung_nmcnr†§ 010_peng_acbc†§ 012_peng_tcfc†§ 013_qu2017_azc†§ 014_ramos_pfc†§ 015_sau_cfcc†§ 016_song_dacfc† 017_tan_clia†§ 018_telescopic_cascode§ 019_ti_ldo_error§ 022_fer_two_stage 023_fer_fd2s§ 024_smcnr†§ 032_ti_ldo_error_selfbias§ 033_ti_ldo_ref_selfbias 025_hsu_classab_ota 026_fan_chopper_ota 027_fan_rrl_ota 031_srmc_core_cmfb

Stages Comp. 1 3 3 1 3 3 3 3 3 3 3 3 3 3 3 3 1 2 2 2 2 2 2 2 2 1 2

none RAFFC SMC none AFFC DFCFC1 DFCFC2 NMCF NMCNR ACBC TCFC AZC PFC CFCC DACFC CLIA none none miller miller_nulling miller_nulling none none miller-rz miller None miller-rz

BW Gain (dB) UGF (MHz) PM (◦ ) CMRR (dB) PSRR (dB) Power (µW) Gate area (µm2 ) vn,in vn,in

27.9 90.1 191.7 77.6 64.0 163.6 152.5 172.4 159.6 162.5 155.2 121.8 184.1 150.9 63.4 75.4 82.7 43.0 69.7 78.9 116.0 72.7 74.1 39.9 27.1 71.4 65.9

0.02 3.75 1.02 10.77 1.88 1.32 1.48 0.77 2.44 0.51 1.12 2.61 0.50 6.76 7.71 2.58 0.48 6.32 9.54 16.05 0.08 18.65 7.29 0.36 0.63 1.36 7.80

90.1 84.4 56.9 87.1 65.1 66.1 63.7 62.9 67.7 70.5 66.5 65.4 67.4 95.5 81.0 51.7 89.9 91.4 66.5 62.6 65.7 82.7 74.1 124.7 75.0 87.9 68.9

51.0 89.2 95.6 121.7 131.3 96.6 116.6 110.6 97.8 116.6 85.9 70.9 110.2 100.1 48.7 124.0 95.0 42.0 49.3 102.9 72.0 61.7 43.2 118.0 62.6¶ 132.1 >180

53.5 63.4 59.4 83.5 75.3 60.6 64.1 57.6 70.3 53.3 60.5 70.5 52.3 85.3 57.5 86.4 82.3 67.7 49.5 108.9 71.6 56.0 54.1 75.4 -0.9¶ 66.3 125.4

30.5 422.5 2102.8 998.4 857.2 1905.3 729.4 700.9 588.1 191.6 323.7 264.6 2294.4 1688.8 587.3 166.5 11.5 7497.1 226.4 584.8 1.2 590.0 390.5 1752.1 920.9 463.0 985.0

THD

40 206.2 57.7 8.743 8419 25.1 55.0 0.005 107196# 12.7 12.7 0.153 918 23.9 42.7 <0.001 147597# 27.2 38.5 0.128 164833# 27.0 36.3 0.001 31709 35.5 52.3 <0.001 47396 25.1 20.4 0.033 24595 22.3 63.0 <0.001 22939 46.4 28.6 <0.001 24526 41.4 43.7 0.002 21107 50.5 92.2 0.680 277287# 10.7 5.8 0.001 36759 23.5 64.2 4.082 10302 149.8 240.2 0.037 27722 117.4 218.1 0.093 71 49.8 38.5 0.029 302 31.5 38.0 0.429 176 46.0 80.0 1.767 95 82.1 112.0 0.004 332 581.2 74.6 1.544 460 19.4 48.0 0.011 331 18.0 38.7 0.304 3406 28.2 21.2 – 2369 36.7 29.8 3.270 1317 46.1 49.8 <0.001 14 65.2 82.5 –

20

— and – mark a cell with no value: not applicable, not recorded in this configuration, or a recorded bench failure. † AnalogGym-sourced. § Re-sized after failing cross-kit verification. 004_folded_cascode retains its recorded values, but its deck does not simulate on this kit at the archived revision (an unresolved device-model defect), so they are not reproducible here; 017_tan_clia was re-sized on this kit and its released point is stable (+51.7◦ ). Rejection readings at or above 180 dB sit at the AC solver’s resolution floor and are printed as bounds; every CMRR/PSRR figure is systematic (mismatch excluded), an upper bound (§III-B4). # Constrained re-optimizer output, stability-feasible only above 0.1 mm2 of summed gate area, an optimizer artifact rather than a defensible design; no marked row passes its full datasheet, so none enters the validated set of Fig. 4. Fully-differential rows report the systematic CMRR/PSRR (mismatch excluded), measured on the common-mode path with the differential gain folded in. ¶ Chopper core characterized with its output chopper held static; chopping leaves the CM path unchanged, and with no CMFB the rejection is CMFB-limited. Adding one (034_fan_chopper_cmfb) improves both CM-path columns by 43.4 dB on ihp-sg13g2 for 0.8 dB of differential gain. PM is the stb loop-probe reading (pm_loop_deg) where that bench’s unity crossing agrees with the AC sweep to within 20 %, and the AC-sweep reading (pm_deg) otherwise; either is folded into (−180◦ , 180◦ ]. Here 26 of the 27 tabulated PM cells are the stb loop-probe reading and the rest are the AC sweep. Both readings are carried per design point in the released scoreboard. Both noise columns are µVrms ; THD is % (single-tone, 0.1 V, or 0.05 V where the swing would clip, at a per-cell frequency set from its UGF, harmonics 2–5). Gate area is the summed gate area of the sized devices only; capacitor and resistor area is excluded (§III-C). 017 is tabulated for information but excluded from the counted corpus; the counted 028 (behavioral) and 029 (no recorded baseline) are not tabulated. The ∼10 mW of 019_ti_ldo_error is design intent: the source design’s 1 mA reference is mirrored at near-unity ratio into the tail and output legs. 031_srmc_core_cmfb carries the same gate area on ihp-sg13g2 and gf180mcu because the gf180mcu binding ports the ihp geometry unchanged. BW each cell’s own 1 Hz–UGF band; the uniform band overstates a slow cell (up to 7.8×) and understates a fast one (down to 0.17×). vn,in integrates the uniform 1 Hz–1 MHz comparison band, vn,in Withheld entries: for each, no sizing was found that is both stable and within specification, so no design point is claimed. 011_peng_iac – the only stabilizing sizing found sacrifices 37 dB of PSRR and violates its specification; 021_yan_az – self-oscillates at 1.84 Vpp with the input held at DC; the oscillation arises inside the cell, where no outer compensation reaches it.

ANALOG-DB: AN AGENT-FIRST ANALOG INTEGRATED CIRCUIT DATABASE

TABLE X A MPLIFIER /OTA BENCHMARK IN GF180MCU ( G F 180 M C U ): EVERY AMPLIFIER BOUND TO THIS KIT WITH A RECORDED AC BASELINE , AT ITS RELEASED SIZING . A LL VALUES ARE RE - SIMULATED UNDER UNIFORM CONDITIONS (CL =10 P F, UNITY- GAIN BUFFER ; NOISE 1 H Z –1 MH Z ; THD PER THE FOOTNOTE ).

Circuit 001_5t 002_alfio_raffc†§ 003_fan_smc† 004_folded_cascode 005_hoilee_affc†§ 006_leung_dfcfc1†§ 007_leung_dfcfc2† 008_leung_nmcf†§ 009_leung_nmcnr† 010_peng_acbc† 011_peng_iac†§ 012_peng_tcfc†§ 013_qu2017_azc† 014_ramos_pfc† 015_sau_cfcc†§ 016_song_dacfc† 019_ti_ldo_error§ 021_yan_az†§ 022_fer_two_stage§ 023_fer_fd2s 024_smcnr†§ 017_tan_clia† 018_telescopic_cascode 025_hsu_classab_ota 026_fan_chopper_ota 027_fan_rrl_ota 031_srmc_core_cmfb 032_ti_ldo_error_selfbias 033_ti_ldo_ref_selfbias

Stages Comp. 1 3 3 1 3 3 3 3 3 3 3 3 3 3 3 3 2 3 2 2 2 3 1 2 2 1 2 2 2

none RAFFC SMC none AFFC DFCFC1 DFCFC2 NMCF NMCNR ACBC IAC TCFC AZC PFC CFCC DACFC none AZ miller miller_nulling miller_nulling CLIA none miller-rz miller None miller-rz Rz+Cc∗ Rz+Cc∗

BW Gain (dB) UGF (MHz) PM (◦ ) CMRR (dB) PSRR (dB) Power (µW) Gate area (µm2 ) vn,in vn,in

26.0 109.6 58.9 59.3 91.9 122.9 102.4 116.0 114.6 90.7 129.5 106.8 94.2 135.9 — 84.0 41.1 153.7 66.9 81.3 93.3 118.3 57.5 47.5 79.9 58.7 87.6 77.0 78.5

0.30 2.06 2.72 1.77 2.56 2.18 1.79 2.97 1.22 0.91 4.07 2.17 2.90 1.46 — 1.22 68.10 5.17 10.28 21.16 0.12 1.97 1.80 0.35 7.75 0.15 33.20 9.75 6.40

90.5 68.5 88.8 90.4 109.8 87.4 86.0 65.5 82.2 88.2 80.5 81.7 88.6 83.9 — 103.3 58.0 119.2 68.1 67.0 67.4 78.5 87.7 51.0 64.0 89.8 81.3 89.8 72.7

21.7 80.1 36.5 48.2 50.7 80.8 80.5 44.5 100.1 43.7 98.1 93.0 80.8 111.9 63.6 64.0 45.5 59.6 69.2 107.3 68.9 81.5 61.3 114.5 16.7¶ 93.1 >180 62.4 44.9

26.8 78.2 20.6 43.8 43.0 65.8 59.3 44.1 61.9 42.7 71.2 65.9 28.4 59.1 50.4 39.1 47.9 61.6 74.5 112.6 69.0 60.4 57.5 130.2 -1.2¶ 89.6 >180 56.4 46.5

36.1 677.4 1473.9 177.7 209.2 488.5 429.3 326.1 111.4 424.5 91.8 213.0 76.1 685.6 255.4 225.2 10267.6 126.1 250.4 557.2 2.3 29.0 21.7 13.1 310.1 8.2 205.0 110.7 73.3

THD

24 147.7 122.2 7.511 28122 57.9 89.9 0.642 412 257.5 300.3 0.272 1300 99.1 114.2 0.472 315 182.8 219.8 0.117 2139 61.0 81.6 0.001 440 101.5 143.4 0.003 1128 99.2 145.9 0.122 272 119.1 128.3 0.001 240 215.3 209.4 0.118 835 125.0 190.0 0.001 1210 104.3 137.1 0.001 204 272.1 376.4 1.338 2583 33.1 39.6 0.002 254 132.2 – 0.586 472 583.2 612.6 0.355 524 42.9 86.0 0.128 144 182.1 226.5 3.441 176 91.6 138.6 0.162 92 102.3 158.4 0.003 355 374.7 93.5 0.412 7669 280.9 337.9 0.082 360 40.3 46.2 0.028 123 236.7 191.3 – 216 89.1 132.0 <0.001 476 125.6 65.4 0.203 141 44.3 91.8 – 1455 54.6 103.3 0.014 343 53.4 79.3 0.242

21

— and – mark a cell with no value: not applicable, not recorded in this configuration, or a recorded bench failure. † AnalogGym-sourced. § Re-sized after failing cross-kit verification. The imported 002_alfio_raffc sizing limit-cycled through its RAFFC inner loop and was re-sized; it meets every specification except its slew-limited 1.86 µs settling time. 017/018 are re-sized inside the kit’s device-model bins and reported as measured. ∗ Abbreviated compensation scheme: Rz+Cc = “Rz + Cc from the first-stage node to the output”. Rejection readings at or above 180 dB sit at the AC solver’s resolution floor and are printed as bounds; every CMRR/PSRR figure is systematic (mismatch excluded), an upper bound (§III-B4). Fully-differential rows report the systematic CMRR/PSRR (mismatch excluded), measured on the common-mode path with the differential gain folded in. ¶ Chopper core characterized with its output chopper held static; chopping leaves the CM path unchanged, and with no CMFB the rejection is CMFB-limited. Adding one (034_fan_chopper_cmfb) improves both CM-path columns by 43.4 dB on ihp-sg13g2 for 0.8 dB of differential gain. PM is the stb loop-probe reading (pm_loop_deg) where that bench’s unity crossing agrees with the AC sweep to within 20 %, and the AC-sweep reading (pm_deg) otherwise; either is folded into (−180◦ , 180◦ ]. Here every tabulated PM cell is the stb loop-probe reading. Both readings are carried per design point in the released scoreboard. Both noise columns are µVrms ; THD is % (single-tone, 0.1 V, or 0.05 V where the swing would clip, at a per-cell frequency set from its UGF, harmonics 2–5). Gate area is the summed gate area of the sized devices only; capacitor and resistor area is excluded (§III-C). 017 is tabulated for information but excluded from the counted corpus; the counted 028 (behavioral) and 029 (no recorded baseline) are not tabulated. The ∼10 mW of 019_ti_ldo_error is design intent: the source design’s 1 mA reference is mirrored at near-unity ratio into the tail and output legs. BW each cell’s own 1 Hz–UGF band; the uniform band overstates a slow cell (up to 7.8×) and understates a fast one (down to 0.17×). vn,in integrates the uniform 1 Hz–1 MHz comparison band, vn,in

ANALOG-DB: AN AGENT-FIRST ANALOG INTEGRATED CIRCUIT DATABASE

TABLE XI A MPLIFIER /OTA BENCHMARK IN SKY130 ( S K Y 130): EVERY AMPLIFIER BOUND TO THIS KIT WITH A RECORDED AC BASELINE , AT ITS RELEASED SIZING . A LL VALUES ARE RE - SIMULATED UNDER UNIFORM CONDITIONS (CL =10 P F, UNITY- GAIN BUFFER ; NOISE 1 H Z –1 MH Z ; THD PER THE FOOTNOTE ).

ihp-sg13g2

Circuit 001_analoggym_basic†¶ 002_analoggym_folded_cascode†¶ 003_analoggym_simple†¶ 004_basic_pmos¶ 005_buffered_ref¶ 007_pmos¶ 008_fer_mirror_ota 009_fer_5t_pass¶

Load reg. (mV)

Line reg. (mV)

PSRR (dB)

PM (◦ )

Undershoot (mV)

Iq (µA)

Gate area (µm2 )

26.3 11.6 12.5 25.1 1.3 15.7 28.0 35.6

4.0 0.8 2.9 9.5 4.3 4.7 2.0 0.4

37.0 48.4 35.2 37.4 44.5 43.9 49.5 60.9

89.5 97.7 136.0 89.3 46.4 87.0 53.7 90.3

161 632 301 9 2 4 41 19

89.1 408.1 286.1 206.5 758.7 232.4 164.0 73.9

4837 2181 1758 790 779 608 162 53

Load reg. (mV)

Line reg. (mV)

PSRR (dB)

PM (◦ )

Undershoot (mV)

Iq (µA)

Gate area (µm2 )

51 101 169 48 340 266 99 179

15.8 4.8 59.1 11.9 6.0 5.4 39.0 24.3

1.4 0.6 6.3 0.2 17.2 0.6 2.5 0.5

46.6 47.9 29.2 71.7 35.6 69.1 37.4 62.0

91.4 94.1 89.7 87.7 52.6 49.7 35.3 87.5

237 724 994 6 5 7 56 13

84.2 385.4 114.2 206.5 472.4 145.6 103.9 64.9

6663 1460 3748 396 900 1489 201 263

Vout (V) Dropout (mV)

Load reg. (mV)

Line reg. (mV)

PSRR (dB) PM (◦ )

Undershoot (mV)

Iq (µA)

Gate area (µm2 )

692.5 3.6 100.8 12.8 10.7 17.4 26.1

241.0 0.3 10.8 0.8 0.5 1.1 0.3

1243 732 920 6 9 59 12

19.0 268.9 108.4 206.5 86.3 101.4 64.5

4463 1425 3738 549 1260 162 117

Vout (V) Dropout (mV) 1.60 1.81 1.81 1.31 1.61 1.22 1.21 0.91

48 52 148 41 170 99 76 189

gf180mcu

Circuit 001_analoggym_basic†¶ 002_analoggym_folded_cascode†¶ 003_analoggym_simple† 004_basic_pmos¶ 005_buffered_ref¶ 007_pmos¶ 008_fer_mirror_ota 009_fer_5t_pass¶

Vout (V) Dropout (mV) 1.60 1.80 1.84 1.31 1.64 1.20 1.21 0.91

ANALOG-DB: AN AGENT-FIRST ANALOG INTEGRATED CIRCUIT DATABASE

TABLE XII LDO BENCHMARK ACROSS THE THREE OPEN PDK S AT THE RELEASED SIZING OF EACH ENTRY ( TT CORNER ; TOP : I H P - S G 13 G 2, MIDDLE : G F 180 M C U , BOTTOM : S K Y 130). A LL VALUES ARE RE - SIMULATED , AND EVERY ENTRY PASSES ITS FULL DATASHEET AGAINST THE PER - ENTRY BANDS AND OPERATING CONDITIONS OF TABLE VII.

sky130

Circuit 001_analoggym_basic† 002_analoggym_folded_cascode† 003_analoggym_simple† 004_basic_pmos¶ 007_pmos¶ 008_fer_mirror_ota¶ 009_fer_5t_pass¶

1.60 1.80 1.87 1.30 1.21 1.21 0.92

258 82 174 58 238 63 355

8.9 53.2 25.4 64.2 70.1 37.1 63.4

91.8 98.1 90.5 86.6 65.1 47.8 88.3

† AnalogGym-sourced. ¶Re-sized by the per-role g /I m D loop. 005 carries no sky130 binding and the stub ldo_006 is excluded; 007 sits outside the counted corpus of Table III but its three bindings are

tabulated, giving the twenty-three rows. As a capacitor-less regulator switching 5–55 mA into 50 pF, 001 has an intrinsically large undershoot, inside its deliberately relaxed bands. Judged against one class-level reference band (Vout within ±5 % of nominal; load and line regulation each ≤ 5 % of Vout ; PSRR ≥ 20 dB at 1 kHz; dropout ≤ 300 mV; loop phase margin ≥ 45◦ ; Iq ≤ 10 % of nominal load), 10 of the 23 bindings are within the band: the failures concentrate in the Iq (10 of 23) and load regulation (2 of 23) sub-bands, while 19 of 23 meet the Vout /regulation/PSRR/dropout core. Nominal here is each entry’s own datasheet target rather than its measured value: nominal Vout is metrics.v_out.spec.typ and nominal load is default_conditions.iload.typical, which is 5 mA for 001, 10 mA for 002/003 and 1 mA for the rest, so the Iq sub-band is a different absolute current on different rows. Every count here is computed from the released scoreboard. 22

Circuit 001_hsu_bandpass_classab 002_fan_chopper_simple 003_fan_chopper_pf 004_fan_chopper_rrl 005_hsu_pga_ideal 006_fan_chopper_cmfb

Gain (V/V)

Zin (MΩ)

19.7c

201.6c

7.0 6.9 19.1 – –

11.8 23.8 6.4 – –

Ripple (mVpp )

Vos res. (µV)

– 402 220

40.3c

< 10−4r – –

<0.1 <0.1 <0.1 – –

Power (µW) Gate area (µm2 ) Notes 10.1 175.7 175.7 217.9 – 186.0

78 103 105 191 – 138

validated 8/8 ripple target unmet (no ripple loop) positive-feedback Zin boost ×2.0 vs. 002 validated 5/5; RRL nulling + CM servo closed ideal-amp PGA, eight-code sweep recordedp CM-closed 002; DC operating point only on this kitm

ANALOG-DB: AN AGENT-FIRST ANALOG INTEGRATED CIRCUIT DATABASE

TABLE XIII I NSTRUMENTATION - AMPLIFIER / BIO -AFE BENCHMARK IN IHP 130 NM ( I H P - S G 13 G 2) AT THE RELEASED SIZING OF EACH ENTRY: TT CORNER , 1.2 V, 50 F F LOAD , 5 K H Z CHOP WHERE CLOCKED .

c Continuous-time entry (no chopper): closed-loop AC gain, static differential Z r in at 100 Hz, and static Vos . Zero-input residual ripple with the ripple-reduction loop active: the deterministic ripple nulled to the numerical floor of a noiseless transient, against ∼0.40 Vpp for 002, which lacks the loop. p Eight-code validation is recorded (gains −0.08 to +17.98 dB, THD 0.0018 %), but those benches are not bound to the scoreboard. m Binds only the DC operating point that proves the common-mode loop closed (520 mV against the core’s unregulated 610 mV); the remaining benches stay on 002 until the variant is sized. The chopped gain of 002/003 is a windowed transient average. The rows are unoptimized reimplementations of the source topologies [8], [47], [46] on ihp-sg13g2, not measurements of the published silicon, which is why the tabulated powers sit well above the 1.8–6.3 µW the sources report.

23

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