Application of curiosity driven exploration methods for hardware interference identification Ludovic Matar 1 , Clément Moulin-Frier1 ,Pierre-Yves Oudeyer1 1
Flowers AI & CogSci Lab - National Institute for Research in Digital Science and Technology, Bordeaux, France {ludovic.matar, clement.moulin-frier,pierre-yves.oudeyer}@inria.fr
arXiv:2609.08729v1 [cs.AI] 8 Sep 2026
Abstract The transition from single-core to multi-core architectures in safety-critical embedded systems introduces significant challenges due to inter-core interference caused by contention for shared hardware resources. Such interference affects execution times and complicates the verification of strict temporal requirements, particularly in domains such as avionics where standards require comprehensive identification of interference sources. Existing interference analysis approaches, whether manual or modelbased, struggle to capture the full range of behaviors arising from the complex interactions among microarchitectural components. In this paper, we frame multi-core interference analysis as the exploration of a complex system behavior space. We propose the use of curiosity-driven exploration algorithms from artificial intelligence to systematically and efficiently cover the space of possible interference behaviors. Using a simulator-based environment, we show that the proposed approach achieves broader and more uniform behavioral coverage within a limited experimental budget compared to traditional pseudorandom program generation methods.
CPU registers
Tiny Capacity Extremely Fast
Static Random-Access Memory
L1 cache L2 cache L3 cache
Low Capacity Faster
Dynamic Random-Access Memory
Main Memory
Medium Capacity Fast
Hard Disk Drives (HDD) Solid State Drives (SSD)
Permanent Storage
Large Capacity Slow
Figure 1: Common computer memory hierarchy [18] Systems on chips face a general trade-off between the necessary time to access information stored in a memory resource and their storage capacity. As an element is closer to the CPU, its access time and storage capacity are smaller. This principle is illustrated in Figure 1. Because they are directly on the CPU, registers typically serve information almost instantly. Their storage capacity is very small, and only essential information is stored. When a core treats a memory instruction, it requests the main memory by default. However, the main memory often operates orders of magnitude slower than the CPU. Thus the cache, namely random static memory locates between the registers and the main memory. It has larger latencies than the registers, but remains considerably faster than main memory. Moreover, it has a higher storage capacity than the registers but smaller than the main memory. It stores areas of the main memory that are the most likely to be referenced. The main memory consists of DRAM cells that offer a great storage capacity. Therefore, there may be a noticeable slowdown each time the CPU needs to access the main memory. As a consequence of this organization, competition for accessing stored data and instructions within shared caches and shared memory between CPU cores increases the execution time, and thus creates potential interference channels.
Keywords: Machine learning, Real-time application, Interference Analysis, Curiosity-Driven Learning
1
Processor
Introduction
The shift from single-core to multi-core architectures is essential in safety-critical embedded systems in multiple domains, such as aerospace and automotive, driven by both the need to enhance processor performance for increasingly demanding applications and adaptation to recent technology. However, this transition introduces new complexities due to tasks running in parallel competing for shared resources; particularly, hardware contention issues known as inter-core interference. As the occurrence of interference has a consequence on the execution time, the use of multi-core processors in critical real-time systems represents a challenge. Indeed, temporal requirements with high levels of confidence have to be met. In the avionics domain, the AMC 20-193 standard requires identifying all sources of interference that can occur when executing tasks in parallel and addressing them.
Definition 1 Interference is a phenomenon such that, for identical initial conditions, the execution time of an application S1 running in isolation (S1 , ) on a platform differs from the execution time of S1 running with an application S2 on the platform (S1 , S2 ). Interference arises from contention on shared resources, e.g., when multiple cores compete to allocate information 1
in cache or memory. Another case is the competition for accessing a shared bus, resulting in bandwidth limitations and delays in data transfer. To summarize, we can distinguish distinct categories of interference occurring because of contention on shared resources [20]:
In this sense, multi-core architectures can be considered complex systems. A complex system is a system consisting of multiple entities interacting non-linearly with each other, giving rise to emergent phenomena that are difficult to predict [19]. Examples of complex systems in Nature are water molecules crystallizing into snowflakes, collective animal behavior forming complex patterns (e.g., bird flocks), or chains of amino acids forming complex 3D protein structures. To study such systems, scientists often need to build a model mapping their input parameters (e.g., a sequence of amino acids) to their corresponding observed behavior (e.g., the resulting 3D shape of a protein). Complex systems often suffer from so-called butterfly effects, where two slightly different initial conditions do not necessarily induce similar outcomes. Such systems also usually exhibit attractor effects, that is, a tendency of the system to evolve towards a particular set of states. Understanding and predicting the behavior of complex systems often requires uncovering the diversity of behaviors they can produce. This is usually a challenging problem, in particular when the parameter space is high-dimensional and when the mapping from the parameter space to the behavior space is highly non-linear. In particular, random exploration of the parameter space is usually inefficient for uncovering the diversity of potential behaviors in most complex systems. Recently, contributions in AI have proposed algorithms able to efficiently cover the space of behaviors of any complex system [9], namely, curiosity-driven exploration algorithms, which belong to the family of automated discovery algorithms. These algorithms have proven to be very efficient at uncovering a wide diversity of behaviors in many complex systems from different scientific domains, including computer science [10], physics [12], chemistry [15] and biology [11]. In this paper, we propose, for the first time to our knowledge, to apply these algorithms to the problem of discovering interference patterns in multicore processor systems. For this aim, we use a multi-core processor simulator, enabling us to prototype our methods without having to deal with the complexity of a real hardware architecture. We show that our proposed method enables better discovery of the space of possible behaviors of the system with a limited experimental budget, compared to more standard methods based on the pseudo-random generation of programs.
• Cache contention: When multiple cores compete for space in shared caches, evicting each other’s data and causing cache misses. • Memory contention: When multiple cores access a shared memory simultaneously (such as the main memory), leading to a bottleneck due to limited memory bandwidth. • Bus contention: When cores compete for access to a shared bus, resulting in bandwidth limitations and delays in data transfer. • I/O Contention: When multiple processes try to perform I/O operations at the same time, leading to delays and reduced I/O performance. As there are multiple types of interference, there exist various types of interference sources to discover. In the following, we will briefly present existing methods that tackle real-time system challenges. Various methods have been proposed to identify mechanisms that are sources of interference [14, 6, 8]. Classic interference analysis methods are either manual and empirical approaches or model-based approaches. The first ones involve manually analyzing the hardware documentation or further characterizing the hardware through experiments and measurements [3, 13, 22, 8, 16]. The others involve identifying interference from a model of the system through two principles: (1) capturing the hardwarelevel knowledge about the system to produce a model, and (2) using an analyzer tool which identifies the interference channels from the model [6, 2, 5]. Classical approaches to interference identification rely heavily on analyzing hardware datasheets, which are often large [17], complex, incomplete, or inconsistent. This makes the process difficult and error-prone, leading to uncertain results and possibly missed interference channels. This can lead, for example, to creating oversimplified models or test cases, resulting in missed interference scenarios or channels [7]. While existing approaches have enabled better anticipation of potential sources of interference, they remain limited in their ability to cover the entire space of possible behaviors of multi-core processor systems. Interference patterns arise from the complex non-linear interactions between a large number of micro-architectural components. In consequence, they are extremely sensitive to small variations in the concurrent programs that are being executed, which strongly limits the ability to predict the behavior of the systems analytically. Moreover, programs that are generated with pseudo-random procedures are unlikely to cover the entire space of possible behaviors.
• In section section motivation, we recall general principles regarding interference. • Then in section 2, we highlight previous related AI works on real-time systems. • In section 4 we unfold our exploration strategy step by step. • In section 5, we present a summary of our findings, with results of diversity measures. 2
2
Related works
The interest in AI techniques within the real-time computing community is relatively recent. Although studies tackling interference on embedded platforms using AIbased techniques exist, to our knowledge, no studies have explicitly targeted their use to identify sources of interference. Nevertheless, we will review the key works in these related areas and explore how they might be adapted or inspire solutions for our problem. Several works have focused on the use of Machine Learning to estimate Worst-Case Execution Times, whether for single-core platforms [1] or multi-core ones [4]. An interesting work closer to our objective is the Kryptonite approach [21], introducing a framework that synthesizes a maximally interfering environment for a Program Under Test (PUT) executing on a multi-core platform. In other words, the Worst-Case Program Interference is targeted. The approach relies on a set of code snippets, called gadgets, to hammer specific shared resources in the multi-core platform and create interference. Kryptonite then arranges the gadgets in order to maximize interference in two phases: firstly, a greedy approach is used to iteratively build a sequence of gadgets that increases execution times of the PUT. And secondly, a Reinforcement Learning (RL) algorithm is used to finetune the interfering environment. Although the objective is not the same, this approach motivates the idea of using an automated discovery algorithm on a multi-core platform to explore interference as it requires many interactions with the system. Indeed, a complex system is exploited, and the objective of reaching an optimum in an output space by exploring a code space is fulfilled. In contrast with an optimization method that minimizes a loss function, we propose a space coverage technique to induce a large diversity of behaviors in a given complex system. In the next section, we present our basic simulator upon which we will perform our exploration.
Core 0
Core 1
Cache L1
Cache L1
Shared cache L2
DDR Memory Controller DDR Memory
Figure 2: Simulated dual-core architecture used in this paper. Each core has a private L1 cache and shares an L2 cache with the other. The L2 cache is connected to the main DDR memory via its DDR memory controller. With such a configuration, interference arises in shared components, such as the L2 cache, the DDR memory controller, and the interconnect. In the following, we explain the functioning of some of the basic blocks of our simulator.
3.1
Core model
As interference is mostly due to memory mechanisms, the simulation of cores handles exclusively memory access instructions; that is, the instruction set is reduced to read and write operations in memory since, ultimately, only memory accesses are simulated. In the following, we denote the ”read” operations by RD and the ”write” operations by WR. In our algorithms, for each core, a simple loop models the ”fetch and execute” cycle. At each CPU cycle, the core can: 1. wait for the end of an RD operation, 2. execute an RD,
3
Description of our dual-core model
3. execute a WR, 4. execute an instruction that does not perform memory accesses, which, in the case of the simulator, amounts to doing nothing.
We justify the implementation of the simulator and briefly describe components and their behaviors. A minimum of two cores with shared memory components is, by definiAs in real-life applications, we make use of a set of tion, necessary to induce interference phenomena. Thus, virtual addresses that maps to the set of physical adour basic simulator model contains: dresses, that is, elements of the micro-architecture memory. Within our programs, virtual addresses are simply • two cores, modeled as numbers. The function that associates a virtual address to a location in the DDR memory is given in • their respective private L1 caches, A. Within the pairs, the programs do not exchange data • a shared L2 cache unit and a DDR memory with its to be written or read, but are to be executable and incontroller, terpretable; moreover, this data is not modeled as it • an interconnect model that transmits instructions does not play any role in interference phenomena, as opposed to instructions. Programs consist of RD and sent by the cache to the memory. 3
WR at given addresses. The shipment is done via the private L1 caches, as instructions are not stored in either the cache or the memory. Thus, programs are concretized as simple dictionaries with the format {cycle:(type,address)} as follows. For each instruction in a program, its key is the cycle at which the considered instruction is sent to the simplified simulator.
Command Transition
IDLE
Automatic Transition
ACT
Activate Bank Row
WR
RD
Listing 1: Example of simplified assembly programs. program_0 = {23:( ’ read ’ , 11) ,37:( ’ read ’ ,17) ,49:( ’ write ’ ,6)} program_1 = {12:( ’ write ’ , 24) ,18:( ’ read ’ ,39) ,32:( ’ write ’ ,37)}
WR
RD Bank Row Active
Writing RD
Reading WR
The maximum length of a program and the largest cycle for which an instruction is sent are fixed as parameters. This model is obviously very simplified compared to the actual operation of a physical target device. Waiting for the completion of a read memory access to continue code execution does not correspond to reality because the Figure 3: Simplified state diagram assuming a single bank processor has various mechanisms specifically allowing it [14] to hide these latencies. This wait is only necessary to preserve true data access dependencies (e.g., a program WR @x RD @x must be executed in this order and be 3.2.1 DDR model preserved at run time to maintain program semantics). PRE
PRE
PRE
Precharging
3.2
Let’s recall that DRAM is organized in rows and columns of banks. Each bank contains an additional row called a row buffer. When information is accessed, its row is stored in the row buffer. In our model, the memory consists of several banks, each of which contains a row buffer acting as a cache. Latencies are modeled and play an important role in the interference delay in the following way:
Cache model
Each cache level is configurable in total size, cache line size, and associativity. By default, the behavior is of the ”write-back” type, that is, writing to lower-level memory occurs when a cache line is evicted. During the write operation, the line is simply marked as ”dirty” and is written to the lower-level memory during its eviction. It is also possible to employ a ”write-through” behavior in which writing to the lower-level memory is done immediately. The management of the eviction of cache lines is carried out by a PLRU whose role is to determine the line to be replaced based on the current state of the cache. Ideally, we would like to implement a behavior of the LRU (Least Recently Used) type, which would consist of eliminating the line used least recently in order to make the most of the locality principle 1 . However, this strategy is expensive to implement and we often prefer to use a simpler mechanism called Pseudo-LRU, which relies on a binary tree.
• Access to different rows from the same bank induces significant delays because of the temporal cost of changing rows in the buffer. • Simultaneous accesses to distinct rows from the same bank induce larger temporal costs than simultaneous accesses to distinct banks. In other words, intrabank interference induces larger delays than interbank interference.
Each bank is managed by a timed state machine that reproduces the one described in [14] (see figure 3). The state of the banks of the DDR determines the completion dates of operations. Requests are issued by the DDR controller. Let’s note PRE as the operation that deactivates an open row of a given bank; this action writes the selected information from the row buffer to the memory. Thus, this algorithm includes a function that maintains And ACT is the operation that activates a closed row by the data structure with a binary tree and which allows storing the information from the given row in the buffer. choosing the next row to be evicted based on memory Additional information on the DDR is given in A. accesses. It also includes a function allowing the choice of the next cache row to be evicted using the information 1 According to the spatial locality principle, data is very likely to contained in the binary tree. The last level cache (L2 in be accessed when one of its neighbors has recently been accessed, figure 4) is shared by both memory hierarchies. There is whereas according to the temporal locality principle, recently accessed data is very likely to be accessed again.[8] no cache coherency management mechanism. 4
3.3
DDR controller model
discover a large diversity of possible interference patterns. We wish to explore a behavior space B that characterizes interference patterns within the hardware by manipulating inputs from a parameter space Θ; see Figure 4. In our case, we establish a parameter space made of simplified assembly programs. It is essential, on the one hand, to formally model basic elements of the exploration, such as the parameter space Θ and the behavior space B, and on the other hand, to specify the agent’s internal models.
The memory controller is in charge of reordering memory access requests to maximize the memory access rate. It implements several queues: a queue for commands, a queue for read data, and a queue for the data being written. Prioritization rules are modeled. Indeed, the RD are prioritized over the WR in order to minimize waiting times, while preserving memory consistency (WR @x RD @x must be executed in this order). Instructions targeting lines that are already in row buffers are prioritized in order to avoid the penalty related to completing a PRE=>ACT sequence. RD and WR are processed in ”batches” to avoid the overhead related to the transition between RD and WR. Mechanisms of our DDR controller are described in A.1.
Definition 2 We call a ”pair of programs” a couple of two programs of code S1 and S2 allocated respectively to the C1 and C2 cores of an execution platform. S1 and S2 are independent code programs. In particular, they do not exchange data. Definition 3 We call an ”experiment” the interaction
4
Overview of the exploration with our complex system. It involves the parallel execution of the programs S1 and S2 , and the execution of S1 strategy and S2 alone. All experiments are to be independent; this involves, for example, clearing the cache, DDR, and interconnect before every execution. Core 1 Cache L1
Shared cache L2
From an IMGEP perspective, an element of a behavior space is seen as a goal to achieve; thus, goals are target behaviors in the behavior space. In our experiments, a goal is a vector encoding a targeted interference pattern. The discovery agent samples goals to solve and uses its strategy to solve them. Two internal models are used for these respective aspects: one for the goal generation strategy G, and a goal strategy achievement model Π. As illustrated in Figure 5, the agent fills a database H to update its internal models during the exploration, and thus the acquired data is reused to extract potential solutions to solve other goals. An IMGEP is a loop algorithm that iterates online by interacting with the considered complex system. The algorithm starts with a warming set of Ninit iterations. This helps the exploration to escape poor knowledge regions. This type of architecture highlights previous independent experiments stored in the database H. Using efficient sampling methods, this algorithm allows one to quickly reach a great diversity of outcomes in the behavior space. Moreover, its usage of the database prevents forgetting during exploration.
Miss core 0
Core 0 Cache L1
DDR Memory Controller DDR Memory
Delay core 0 Pairs of programs space Θ
Behavior space B
Figure 4: Illustration of a complex system associated with multi-core hardware. On the left side of the figure, pairs of simplified assembly programs are represented in the parameter space Θ. Each of them is executed on the platform and corresponds to an outcome (behavior) on the right-hand side, representing the behavior space B. In our case, both the parameter space and the behavior space can be high-dimensional spaces, although in general, the parameter space has a larger dimension than the behavior space. The Intrinsically Motivated Goal Exploration Process is an instance of automated discovery algorithms. This diversity-driven strategy aims to maximally cover a behavior space. During its exploration, a discovery agent iteratively samples goals uniformly in the behavior space and offers appropriate parameters to reach them by leveraging previously found (parameters, outcome) relations. The diversity maximization is a side effect of the goal exploration process. The exploration consists of several episodes called ”experiments,” during which the agent continually improves its ability to discover new singularities. For interference identification, the considered complex system is the simulated hardware platform. In contrast to Kryptonite, for example, which attempts to minimize/maximize interference delays, an IMGEP instead aims to
4.1
Parameter space
A pair of programs is required to run each experiment. As presented in Figure 5, the discovery agent generates a pair θ ∈ Θ at each iteration. Following the general program constraints discussed in part 3.1, we recall that most sources of interference are due to memory mechanisms; therefore, we choose to produce pairs of simplified assembly instructions to constitute a parameter space Θ. Indeed, as presented before, only memory instructions 5
2) Use goal achievement strategy model Π to generate a pair of programs θ to reach g, using database H
Miss core 0
Miss core 0
1) Sample a goal g in space B using module G, and database H
θ
g
Delay core 0
Delay core 0
Parameter space Θ (Pairs of programs)
g
Program space Θ
Behavior space B (Perf. counters)
Behavior space B
3) Execute the pair of programs θ
6) Update models Π, G using H 5) Store tuple (g, θ, z) in the database H
4) Observe and characterize outcome z
Miss core 0
z θ
g Delay core 0
Program space Θ
Behavior space B
The process repeats N times
Program space Θ
Behavior space B
Figure 5: Schematic view of an IMGEP for our case of interference identification, based on the general description of IMGEP B. RD and WR are modeled. To get closer to a real-life application, we can model two distinct sets of addresses for the cores, i.e., core 0: 0,20 and core 1: 21,40. As two distinct addresses can map to the same physical address, it will still be possible to observe interference. With the maximum program length and largest shipment cycle being carefully chosen, we synthesize a parameter space of a reasonable cardinality to thus have a better understanding of the results.
Such performance counters can be clock cycles, row misses, instruction types, branch mispredictions, and the number of stalls. Indeed, the phenomena quantified by those performance counters allow for the description of conflicts occurring in shared resources and thus are directly related to interference. In general, information on the platform will always be needed in a context where interference is being addressed. If a platform is a black box, all the requirements of the certification file cannot be fulfilled.
Each element of the established behavior space is perceived as a potential goal for the discovery agent. A goal All microarchitectural mechanisms are known, as the sim- is defined as a pair g = (zg , Lg ) with an embedding zg ∈ B ulator is a white box. We wish to identify the ones re- and an evaluation function Lg = D(·, zg ). Ideally, B has sponsible for interference. A set of relevant performance ”good properties” such as being a low-dimensional metcounters provides building blocks for the behavior space; ric space. The metric property is important for the goal achievement strategy of the discovery agent. Indeed, one see table 3. wants to evaluate the distances between some previous experiment outcomes z and a goal embedding zg . For Performance counter Category Description Processor cycles General Number of executed cycles example: Lg (z) = ||z − zg ||2 . This aspect is essential Instructions completed General Number of completed instructions for designing an efficient goal achievement strategy, as Decode stalled General Number of cycles in a waiting status Cache misses Cache Number of cache misses L1/L2 one wants to efficiently select previous experiment outCache store allocates Cache Number of line allocations in L1/L2 comes and their associated parameters that are potenCache demand access Cache Number of requests for L1/L2 tially suited for the generation of new candidate parameDDR store misses DDR Number of DDR stores DDR load misses DDR Number of misses ters.
4.2
Behavior space
DDR demand access DDR store allocates
DDR DDR
Number of requests Number of line allocations
Because interference arises following microarchitectural behavior conflicts, we target shared resource performance counter differences in values between the executions in isolation (iso) and the executions
Table 1: Set of available performance counters in the dual-core simulator 6
Features Processor cycles diff core Processor mutual Cache write misses Cache write hits Cache read misses Cache read hits DDR misses DDR hits
Category General General L2 Cache L2 Cache L2 Cache L2 Cache DDR DDR
Description Difference [nb of executed cycles][non-iso] − [nb of executed cycles][iso.] Difference [nb of executed cycles][non-iso. core 0] − [nb of executed cycles][non-iso core 1] Difference [nb of L2 cache misses][non-iso] − [nb of L2 cache misses][iso.] Difference [nb of L2 cache hits][non-iso] − [nb of L2 cache hits][iso.] Difference [nb of L2 cache misses][non-iso] − [nb of L2 cache misses][iso.] Difference [nb of L2 cache hits][non-iso] − [nb of L2 cache hits][iso.] Difference [nb of misses][non-iso] − [nb of misses][iso.] for each pair (bank, row) Difference [nb of hits][non-iso] − [nb of hits][iso.] for each pair (bank, row)
We periodically set the sampling boundaries based on the database H, and we simply sample goals with a uniform distribution. For instance, we determine the minima and maxima of the discovered values for each 1dimensional feature:
Table 2: Features constituting the behavior space B. For any performance counter C, we calculate two features FC as non-iso. vs. iso. differences FC ≡ C[non-iso] − C[iso.]. ”iso.” corresponds to an execution with only one of the two cores, 0 or 1.
• minB g := (min{z1 , z ∈ H}, · · · , min{zdim(B) , z ∈ H}) • maxB g := (max{z1 , z ∈ H}, · · · , max{zdim(B) , z ∈ H})
in non-isolation (non-iso). Given a pair of programs, we calculate for each selected performance counter its difference when executing in isolation on one core and in non-isolation on both cores. The features in table 2 constitute the behavior space B. With nbanks banks and nrows rows, the dimension of B is given by n = 3 + 4 · 2 + 2 · 2 · nbanks · nrows and B ⊂ Rn . If nrows = 3 and nbanks = 4, we then have B ⊂ R59 . The performance of the exploration algorithm might decrease in case of a large behavior space dimension as a consequence of the curse of dimensionality, where the interpretation of distances loses its sense. Therefore, working with a parsimonious set of data might imply better results in terms of diversity measures. This chosen configuration of a behavior space is an Euclidean space. Therefore, we can measure distances between the current goal embedding zg and known features z in our database. Let us remark that the performance counters associated with the features presented in table 2 are not systematically available when working with a physical device.
4.3
Then, to establish the slightly larger sampling region, we fix two factors, e.g., f1 = 0.8, f2 = 1.2, that determine percentages of the previous minimal and maximal values for the new uniform distribution that will be used to sample goals g ∈ B. Since G is a multidimensional space, the resulting distribution will be the cartesian product of several 1-dimensional uniform distributions: zg ∼ U([f1 · (minB g)1 , f2 · (minB g)2 ]) ⊗ · · · · · · ⊗ U([f1 · (minB g)dim(B) , f2 · (maxB g)dim(B) ])
4.4
Goal achievement strategy
Expansion
Selection
g
g
Goal sampling Achievement Strategy
with a kNN model
Figure 7: Illustration scheme of a goal achievement strategy. The left hand side illustrates the selection of outcomes stored in the database that will allow expansion, that is the synthesis of a new outcome closer from g (right Sampling region hand side). Here, the two closest neighbors to g in the database H are selected, and their parameters are used Figure 6: Schematic view of a sampling process. Yellow to obtain the new outcome closer to g. points represent border outcomes from the already known We present our population-based achievement strategy, region and allow the determination of the sampling region which resembles an evolutionary algorithm, where the set for the next experiments. of pairs of programs together with their respective outFor the discovery agent, the concept of ”curiosity” is comes is seen as a population. Thus, our algorithm immaterialized by the sampling of goals. For the sampling plies the performance of mutations of the individuals. of goals, the simplest case scenario is to sample them At each step during an IMGEP exploration, the prouniformly at random in a connex subregion of B including grams (parameters) and outcomes ((S1 , S2 ), z) ∈ Θ × B the set of already discovered points. As illustrated in that make up the agent’s discoveries are stored in the Figure 6, choosing the sampling region slightly larger than database H. Because the exploration budget is low, a subregion including the set of already discovered points we choose the agent to perform non-parametric learning, allows to target regions of G that have not been reached which means that the complexity of the model grows linyet but are close to the already discovered ones. early with the size of the database H. Known region
7
5
The goal achievement strategy is typically made of two steps with two respective operators. During the selection step, the discovery agent selects outcomes. The expansion step consists of using their corresponding parameters to produce another one, leading to an outcome close to the goal g, see figure 7.
We run IMGEP for a total of N = 104 iterations, and we initialize it with a warming set of Ninit = 103 iterations of random program synthesis. We choose to run it with k = 1, 2 and 3 as parameters for the kN N model of the goal achievement strategy Π. Each program contains between 1 and 10 instructions. The maximum cycle for the last instruction to be sent is 60. As said previously, we model two distinct sets of addresses for the cores, i.e., core 0: 0,20 and core 1: 21,40. The selection of the simulator parameters chosen to run our experiments is available in A. We first assess the diversity of the resulting datasets through diversity measures. Secondly, we explore the results and attempt to infer diagnostics from the data. Finally, we discuss approaches that would be more relevant for IMGEP.
We use a kN N 2 model as a selection operator. This selection operator relies on an expansion operator, as kNN selects k promising outcomes from H and expands them by producing a candidate pair of programs to achieve g. In particular, we select the k closest outcomes to the given goal g within the database H using a well-designed evaluation function L. We then mix the k corresponding pairs of programs together to obtain a candidate pair of programs to achieve goal g. We establish a weighted evaluation function so that all features are equally considered in the selection step: Lg (z) =
X F
Results
1 2 · (zF − g) , ∀z, g ∈ B maxF − minF
5.1
Diversity evaluation Ddr miss ratio core 0 non−iso vs iso with N=10000. b:bank, r:row 95% asymptotic C.I with n=500
IMGEP k=2 IMGEP k=3
b2,r0
b2,r2
Oper. k=1 Oper. k=2
Oper. k=3
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Random IMGEP k=1
10
2D histogram Diversity
40
For mixing the programs, we select contiguous parts from multiple programs, preserving timing, and ensuring the resulting program fits within the fixed maximum cycle. The length of each segment is chosen at random. The key parameters are the number of segments to produce the output program and the number of programs to mix.
0
To ensure more efficiency, one also apply a mutation operator following the mixing operator. The mutations performed are : 1. randomly change existing instructions, 2. delete random instructions, 3. add random instructions. Consequently, different patterns of the programs change, such as the number of instructions, number of memory accesses, and the set of used addresses.
b0,r0
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Ddr miss ratio core 1 non−iso vs iso with N=10000. b:bank, r:row 95% asymptotic C.I with n=500
IMGEP k=2 IMGEP k=3
Oper. k=1 Oper. k=2
Oper. k=3
25 20 0
5
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In the particular case of k = 1, we simply select the closest observation z of g in the database H and apply the mutation operator to obtain the candidate parameter. The mixing and mutation operators are detailed in B and B.
15
2D histogram Diversity
30
Random IMGEP k=1
b0,r0
During the first iterations of the algorithm, IMGEP typically outputs outcomes that are not diverse. To overcome the difficulty of the agent exploring during its first iterations, a warm-up made of several random iterations is performed. The agent initially induces poor diversity, and while the population stored in the database H grows, the agent is more likely to solve its goals. Hence, on average over time, goals targeted by the agent are not reached with the parameters θ outputted by IMGEP; meanwhile, it is a powerful method that leads to high-diversity discoveries.
b0,r1
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b1,r1
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Figure 8: Diversity of miss ratio for both cores and all bank row pairs. Orange bars represent lower and upper confidence bounds using the Student’s q t-distribution
asymptotic confidence interval P(X̄ − u1− α1 nv̂ ≤ g(θ) ≤ q X̄ + u1− α1 nv̂ ) −→ .95 with mean and unbiased standard deviation estimators. We compare our method with two simple strategies: 1. A random exploration, that is, generating pairs of programs randomly. And 2. to be compared with IMGEP for k, an algorithm that selects k pairs of programs randomly from its database H, mixes them to obtain a single pair,
2 Let’s recall that kN N is a supervised machine learning model that predicts a label y of a given vector x, using the k closest neighbors of x associated labels.
8
and mutates it. Indeed, we would like to ensure that a larger IMGEP diversity does not occur simply because of the design of the mixing and mutation operators. For this matter, we aim to demonstrate that mixing and mutating random selections of programs from the same warming set does not lead to a significantly higher diversity than that of IMGEP runs. The mixing and mutation operators are the same as IMGEP’s. Hence, for a fair comparison, the first Ninit iterations of the random exploration are shared by the IMGEP runs and by the operator combination exploration. We quantitatively assess each exploration process by simply establishing diversity measurements of the outcomes stored in the respective database H. In particular, we observe how the behavior space B is covered by the corresponding outcomes o1 , · · · , on . In the following, we denote two particular subspaces of the behavior space as the time behavior space and hit/miss space. We construct the following measure suitable to assess diversity: The number of bins filled in a n-dimensional histogram. With n = 3 + 4 · 2 + 2 · 2 · nbanks · nrows , being the dimension of each outcome we obtain after an experiment, see part 4.2. We denote the quantity corresponding to each axis j of an outcome F by Fj ∈ R, 1 ≤ j ≤ n. The values of inf(Fj ) and sup(Fj ) are carefully chosen so that ∀F, F ∈]inf(Fj ), sup(Fj )[, and that for every axis j, these values determin the smallest envelopp of possible values. Performance counter Processor cycles Instructions completed Decode stalled Cache misses Cache store allocates Cache demand access DDR store misses DDR load misses DDR demand access DDR store allocates
Inf 0 0 0 0 0 0 0 0 0 0
For each dimension j, we choose the length of bin lj such |x(j)k −x(j)k +1 |
j j that = lj , ∀1 ≤ j ≤ n, ∀kj . D(x(1),··· ,x(n)) 5 is a well-defined positive measure for the associated set of non-empty bins of a data cloud H.
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Figure 9: On the two left plots, we visualize the diversity on the time behavior space and on hit/miss space, that is, how the number of bins filled in a multidimensional histogram increases during exploration. On the right plot, we visualize the diversity of the entire dataset, the dimension of the considered histogram is the number of features (59). Results of N = 104 iterations with a warming set of Ninit = 1000 iterations of random program synthesis
Sup Handmade determined upperbound Maximal number of instructions Maximal number of instructions Maximal number of instructions Maximal number of instructions Maximal number of instructions Maximal number of instructions Maximal number of instructions Maximal number of instructions Maximal number of instructions
For each value of k, which is the number of neighbors in the optimization policy achievement model, we show that IMGEP leads to a higher diversity than the operator combination exploration. Indeed, IMGEP finds many more distinct values of miss ratios across the distinct locations—pairs (bank, row)—in the main memory; see figure 8. Note that the discoveries of ”miss” occurrences probably help to induce more interference. Indeed, whenever requested data is missing in a DDR buffer, it has to be recharged, and this involves an additional delay. Moreover, figure 9 shows that the IMGEP diversity measurement increases faster on the entire behavior space than that of the operator combination exploration, and simultaneously on the distinct L2 & DDR miss/hit and execution time goal subspaces. Generating programs with IMGEP allows one to observe much more interference than generating programs randomly. Interference occurs whenever the execution time in isolation differs from the execution time in nonisolation. To some extent, we consider that a pair of programs produces interference if |time[non-isolation] − time[isolation]| > 0. In the example run presented in
Table 3: Set of available performance counters in the dual-core simulator Let us denote a chosen partition of ]inf(Fj ), sup(Fj )[ by x(j), 1 ≤ j ≤ n with nj points, such that : inf(Fj ) = x(j)1 < · · · < x(j)nj = sup(Fj ). For a family of partitions (x(1), · · · , x(n)), we define a bin as : bin((x(1)k1 , · · · , x(n)kn )) = [x(1)k1 , x(1)k1 +1 [×, · · · × [x(n)kn , x(n)kn +1 [, ∀k1 ∈ N ∪ [1, n1 [, · · · , ∀kn ∈ N ∪ [1, nn [
Miss and hit space diversity, 95% Asymptotic C.I with n=500 1200
Time space mean diversity, 95% Asymptotic C.I with n=500
(1)
We define D(x(1),··· ,x(n)) , the positive measure of data clouds associated with the set of all bins with the partitions x(j). For a set of points discovered H from H, we have: D(x(1),··· ,x(n)) (H) = X = 1{card(bin(x(1)k ,··· ,x(n)k )∩H)>0} (2) n 1 (k1 ,··· ,kn )
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figure 10, the bars with axis 0 on histograms for values of —time[non-isolation] - time[isolation]— demonstrate that exploring the simulator with randomly generated programs produces interference about 4 times out of 10, whereas it is about 7 times out of 10 for IMGEP. Histogram of time differences, core 0
gram on core 0 is executed because of its instructions on cycles 20 and 30 which load the lines {bank 1, row 1} and {bank 0, row 1} into their buffer. Hence, sequences PRE=>ACT are avoided as the data is already in the buffer.
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Listing 2: Example of programs inducing mutual acceleration.
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In Figure 12, we represent values of couples (time[isolation, core 0] - time[non-isolation, core 0], Figure 10: Diversity for execution time behavior space. time[isolation, core 1] - time[non-isolation, core 1]). Any Results of N = 104 IMGEP iterations with k = 1 and point with an abscissa or ordinate different from 0 correa warming set of Ninit = 1000 iterations of random pro- sponds to a pair of programs presenting interference on gram synthesis. core 0 or core 1, respectively. The figure clearly shows that the IMGEP cloud spreads more, indicating that our Information on the execution time is represented for algorithm finds many more interference cases. each program in Figure 11. More precisely, we attribute to each pair of programs executed simultaneously on core 5.2 Analysis 0 and core 1 two respective points on the distinct scatter plots to represent its couple (time[isolation], time[non- The results we presented demonstrate through diversity isolation]). This representation allows us to spot inter- measurements that automated exploration algorithms ference, that is, whenever points are not located on the can cover efficiently an output space of a complex sysred identity line. Points above the red line represent pro- tem associated with a simulated hardware model. The data from which the exploration is performed programs that are slowed down by the parallel execution on the other core, whereas points below the line represent vides only aggregated information and is not internal. programs which are accelerated, which means the exe- While this implies that characterizing sources of intercution time is faster when the program is executed to- ference with such a defined behavior space is limited, we gether with another program. This is due to the absence spot an emerging structure in Figure 13, suggesting that of a coherency management mechanism. For instance, pairs of programs with many requests to the same DDR the following pair of programs results in the acceleration locations induce a greater variety of interference delays. Hence, the resulting pairs of programs causing interferof both programs. One can show DDR bank and line numbers instead of addresses. Instructions of core 1 on ence can be further analyzed by humans, and our method cycles 36, 40, and 41 are processed earlier when the pro- may be completed to ensure that distinct points in the time[non−isolation] − time[isolation], core 1
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fixes its own goals, and on the establishment of a behavior and a parameter space. IMGEP k=1 The results demonstrate that automated discovery alRandom gorithms can interact successfully with a simplified simulated model of dual-core architecture and encourage the idea of exploring a real SoC. Indeed, the behavior space, which consists of performance counters, is explored efficiently with IMGEP, as it leads to a higher diversity than exploring the simulator with programs that are randomly generated. This approach encourages the idea of exploring a behavior space that is more suited for characterizing of mechanisms of interference in order to discover non-trivial −50 0 50 100 time[non−isolation]− time[isolation], core0 sources of interference. In further work, we will aim to develop a strategy that specifically identifies distinct mechaFigure 12: Spanning of IMGEP on time behavior space. nisms that are responsible for interference, rather than exInterference occurs on core 0 or 1 when the abscissa or or- hibiting a large diversity of interferences regardless of the dinate is different from zero. Results of N = 104 IMGEP reasons they occur. For this, we will distinguish whether iterations with k = 1 and a warming set of Ninit = 1000 the observation of an interference relies on the activation iterations of random program synthesis. of a new mechanism. Hence, the objective will be to maximize the number of distinct types of interference. outcome space provide two distinct sources of interference. Delay vs over−lap, core 1
Appendices
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A
Description of our dual-core model
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Category address range address range bank mapping row mapping tRCD (cycle) tRP (cycle) tCAS (cycle) tFRC (cycle) tWR (cycle) tRTP (cycle) tCCD (cycle) tRRD (cycle) nrows nbanks size line size associativity
Description address range for core 0 address range for core 1 Bank mapping for an address a Row mapping for an address a, each row covers 16 addresses Delay induced by an ACT operation, that is, the activation of a closed line, by storing its content in the buffer Delay induced by a PRE operation, that is, the deactivation of an open row for a given bank. Delay to access data after a burst for both RD and WR insttructions. Periodic time for cell refreshments. During this operation, every bank row buffer is precharged Minimum delay between a WR and a PRE operation Minimum delay between an RD and a PRE operation Minimum delay between an RD and a WR operation Maximum delay between two ACT operations Number of rows per bank Number of banks in the DDR Storage capacity of a cache (bytes) Storage capacity of a line (bytes) Number of different cache lines each data block can be mapped to.
Value 0-20 21-40 a%nbanks a//16 15 15 15 30 15 8 4 4 3 4 32,512,512 4,4,4 2,16,16
Figure 13: (time[non-iso] - time[iso]) vs nonoverlap. We call non-overlap the quantity f (p0 , p1 ) = P |(nb access row j , core 0) − (nb access row j core 1)|. j This graph shows the number of access occurring in the Table 4: Selection of the simulator parameters for our same locations for both cores in the main memory is not experiments enough to characterize interference. We believe that creating a space that fully consists of sources of interference will allow discoveries of non-trivial A.1 Complementary information on the DDR and its controller access patterns. In addition, one wants to discover access patterns that are unknown and difficult to produce Our simplified DDR2 model implements the following opby specialized engineers. Furthermore, the resulting be- erations and some are described in 4 havior space would not necessarily be a Euclidean space, and could, for example, be a graph, a tree, or a semantic • WR: Write space. • RD: Read
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• ACT: Activation of a closed row.
Conclusion
• PRE: Deactivation of an open row. This work deals with the problem of interacting with SoCs via automated discovery algorithms to help the discovery • REF: Refreshment of memory cells. of singular cases. The method relies on simple machine learning models to structure an autonomous agent that The functionning of both the DDR and the memory controller are coupled. At each cycle: 11
• The controller determines requests that are achieved, N Number of iterations for the warming set 1000 N −N Total number of IMGEP iterations 9000 that is, if the current date is superior than the sched- k Number of neighbors in the kN N model for the goal achievement strategy Π. 1,2,3 Number of mutations Number of mutation for each program in the model Π 5 uled completion date. In that case, for an RD max sending cycle Maximum cycle for sending the instruction (cycle) 60 Range instructions Minimal and maximal number of instructions 1-10 request, the controller calls a ”call back” function core 0 Range of addresses 0-20 core 1 Range of addresses 21-40 which signals to the core that this access is achieved. This callback is used by the core to allow the execution of a new instruction. No callback functionality Table 5: The selection of IMGEP parameters for our experiments. is not implemented for RD requests. IMGEP parameters
Description
Value
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• The controller treats requests that are located in its Algorithm 1 Random Mixing of Instruction Sequences A list of instruction programs S, number of parts P , entry queue. For each request, it determines whether Require: random seed s, maximum cycle Cmax it can be treated by the DDR according to its state Ensure: A mixed instruction program M Initialize random generator with seed s (handled by the DDR state machine) while ensurChunks ← ∅ ing minimal delay contraints. It then determines the for all program p ∈ S do ”best” request to treat depending on a established Sort instructions of p by increasing cycle ranking to prioritize request inducing ”row hits”, Split p into P contiguous parts for all part q of p do WR over RD requests and arrival order (FIFO polAppend q to Chunks icy). THhe controller finally sends the ”best” request end for to the DDR. Memory accesses are done with burst end for lenght of 8 bytes. Randomly shuffle Chunks Concatenate all elements of Chunks into list L Randomly select |L| distinct cycle values from [1, Cmax ] Sort selected cycle values in increasing order for i ← 1 to |L| do Assign cycle cycles[i] to instruction L[i] end for Construct mixed program M from assigned cycles and instructions return M
The model is inspired from mechanisms described in [14].
A.2
Interconnect model
The interconnect model can be described as follows:
1. It consists in maintainig a queue (FIFO) of memory requests and in executing request in the arrial order and after a delay corresponding to minimale access Algorithm 2 Mutation operator // Mutate an instruction sequence by adding, deleting, or modifying latency. A random relay of 2 cycles in added. 2. At each clock cycle, some number of requests in priority is unpiled from the queue among the ones that are executable during the current cycle. The requests are the, sent to the memory. The number of unpiled requests at each cycle is determined by the bus bandwidth and each the counting of the numberf of treated requests. 3. The requests that could not be treated are moved in the queue of requests that are to be treated in next cycles.
instructions. Require: Instructions θ, Number of mutations N , Maximal cycle c, range for adresses amin , amax ,maximal number of instructions imax ′ Ensure: Initialize a copy θ of the intructions θ Ensure: Initialize set of available cycles freecycles: all cycles - used cycles for i ← 1 : N do ′ if lenght(θ ) > 1 then Select a mutation type : t ∼ U ([add, delete, modify]) else Select a mutation type : t ∼ U ([add, modify]) end if if mutation type is add and freecycles non empty then newcycle ∼ U (freecycles) ′
θ (newcycle) = {new instruction type,a} remove freecycles(newcycle) ′
else if mutation type is delete and lenght(θ ) > 1 then ′
Delete θ (cycle to delete) set free freecycles(cycle to delete)
4. The interconnect clock cycle frequency and that of the cores are the same. One could introduce distinct clocks by calling the functions ”clock” in our codes at distinct cycles.
B
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else if Mutation type is modify and lenght(θ ) > 1 then ′
Goal
Parameters chosen for the IMGEP exploration are described on table 5. We describe below the algorithm designed to mix sequences of simplified assembly algorithms. As a reminder, the algorithms are dictionaries of form {cycle : (type, adress)}. 12
Pick an instruction cycle to modify told , aold = θ (c) modify choice m ∼ U ([type, adress, both]) if m = type then tnew = write if told == read else read θ ′ (c) = {type : tnew , address : aold } else if m address then θ ′ (c) = {type : told , address : U ({amin , · · · , amax })} else //Change both type and address tnew = write if told == read else read θ ′ (c) = {type : tnew , address : U ({amin , · · · , amax })} end if end if ′ if lenght(θ ) > imax then ′
Uniformally sample set of distinct lenght(θ ) − imax instructions to delete Delete the instructions end if end for
B.1
Diversity Evaluation
Another diversity measure, but ill-defined, is the sum of the squared P P euclidean 2distances between all pairs: D(H) = i j≤i ||oi − oj || . This measure is not a well defined positive measure as D(H1 ∪H2 ) ̸= D(H1 )+D(H2 ), when H1 ∩H2 = ∅ in general. However, it provides a good intuition of the diversity, as a small perimeter cloud with small pairwise distances leads to a small diversity result whereas a large cloud perimeter involves larger pairwise distances and thus a larger diversity.
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