arXiv (All)open access
ITP-STDP: A Hardware-Efficient Intrinsic-Timing Power-of-Two Synaptic Learning Engine for On-Chip SNNs
hardware architecture, artificial intelligence, neural and evolutionary computing
This document is indexed with metadata only — full text is not available in the archive for this record.
Open the official source ↗
Related documents
Record · ID 800063
Retrieved via
Conceptio — every document is proof-bundled with source, license, and retrieval metadata.