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A Highly Secure FPGA-Based Dual-Hiding Asynchronous-Logic AES Accelerator Against Side-Channel Attacks

Ng, Jun-Sheng et al.
DR-NTU (Digital Repository of NTU) · Papers
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dualfieldside
other, advanced encryption standard (aes), asynchronous logic (async-logic) design, delay randomizer, dual-hiding, field-programmable gate array (fpga), side-channel attack (sca)
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Record · ID 995761
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