hardware

Documents about hardware

• Evolving hardware-efficient grover circuits with grammatical evolution#431882ULRR
• Hardware-conscious Software Training for Deep Neural Network Inference Accelerator Chips to Recover Accuracy Degradation due to Hardware Variabilities#927559arXiv (All)
• Hardware-Centric Analysis of DeepSeek's Multi-Head Latent Attention#128407arXiv (OAI)
• Hardware-Efficient Error Mitigation and Shot-Efficient Sampling on IBM Quantum Hardware#788535arXiv (OAI Expanded)
• Hardware-Efficient Error Mitigation and Shot-Efficient Sampling on IBM Quantum Hardware#792535arXiv (All)
• Hardware Acceleration of Block-Diffusion LLM for Edge Devices#821064arXiv (All)
• TRACE: Traversal and Reasoning Algebraic Computing Engine for Formal Hardware Verification#622778arXiv (OAI Expanded)
• TRACE: Traversal and Reasoning Algebraic Computing Engine for Formal Hardware Verification#625051arXiv (All)
• Hardware Trojan Threats to Multi-Chiplet Photonic Neural Network Accelerators#974884arXiv (All)
• Hardware-Attributed Operator Profiling for PyTorch#999923arXiv (All)
• Composability rather than computation sets the cost of an analog EML hardware fabric#1011618arXiv (All)
• CovR: Coverage-Aware Hardware Verification via Reasoning-Guided Reinforcement Learning#1013790arXiv (All)
• Hardware-Software Co-Design for Event-Driven SNN Deployment on Low-Cost Neuromorphic FPGAs#682655arXiv (OAI Expanded)
• Hardware-Software Co-Design for Event-Driven SNN Deployment on Low-Cost Neuromorphic FPGAs#684430arXiv (All)
• APEX-RBD: Mixed-Precision Exploration Framework for Hardware-Efficient Robot Dynamics Accelerator Design#972109arXiv (All)
• Harmonia: Algorithm-Hardware Co-Design for Memory- and Compute-Efficient BFP-based LLM Inference#984978arXiv (All)
• Bio-inspired Learning and Decision-Making with Probabilistic In-Memory Computing Hardware: Part 2#998827arXiv (All)
• Securing Processors from Hardware Exploits: A Real-Time Domain Adaptation for Resilient Attack Detection#642192eScholarship
• Fault-tolerant hardware architectures for artificial intelligence algorithms#337572HAL (France)
• HINT: Toward an Executable Hardware-Intent Representation Layer for LLM-Driven RTL Generation#633614arXiv (OAI Expanded)
• HINT: Toward an Executable Hardware-Intent Representation Layer for LLM-Driven RTL Generation#635963arXiv (All)
• LIB-TRAP: Standard Cell Library Hardware Trojan Risk Assessment and Prevention#668600arXiv (OAI Expanded)
• LIB-TRAP: Standard Cell Library Hardware Trojan Risk Assessment and Prevention#670665arXiv (All)
• Atlas: Algorithm-Hardware Co-Design for On-Device City-Scale 3D Gaussian Splatting in VR#920010arXiv (OAI Expanded)
• Atlas: Algorithm-Hardware Co-Design for On-Device City-Scale 3D Gaussian Splatting in VR#924241arXiv (All)
• Confidence-Gated Admission for Hardware Prefetching: When the Gate Matters More Than the Predictor#927504arXiv (All)
• Evolving Layer-Specific Scalar Functions for Hardware-Aware Transformer Adaptation#971804arXiv (All)
• MAGNETIC TUNNEL JUNCTION-BASED STOCHASTIC HARDWARE FOR NEURAL AND ARTIFICIAL INTELLIGENCE SYSTEMS#254783ScholarBank@NUS
• Beacon: LLM Multi-Agent Driven Hardware Design Space Exploration for Heterogeneous Multi-Chiplet Deep Learning Accelerators#808974arXiv (OAI Expanded)
• Beacon: LLM Multi-Agent Driven Hardware Design Space Exploration for Heterogeneous Multi-Chiplet Deep Learning Accelerators#818966arXiv (All)
• H3DNAS: Hardware-Aware ONNX-Native 3D Point Cloud Model Compression#920590arXiv (OAI Expanded)
• H3DNAS: Hardware-Aware ONNX-Native 3D Point Cloud Model Compression#924824arXiv (All)
• Implementación en hardware de una arquitectura híbrida NTT y FFT, para algoritmos de criptografía post-cuántica y procesamiento de señales#431669RID-UNRN
• AI Hardware Accelerators for Large Language Models: Architectures and the Memory Wall#783225arXiv (OAI Expanded)
• AI Hardware Accelerators for Large Language Models: Architectures and the Memory Wall#784815arXiv (All)
• Locus: A Framework for Exploring and Optimizing Point Addition Hardware for Zero-Knowledge Proofs#1013004arXiv (All)
• Hardware-in-the-Loop Evaluation of Sensor-Source Selection for Prosthetic Locomotion Intent Recognition#481828DigitalCommons@CalPoly
• Hardware-aware neural networks#680731Spiral
• TrojanGYM: A Detector-in-the-Loop LLM for Adaptive RTL Hardware Trojan Insertion#633381arXiv (OAI Expanded)
• TrojanGYM: A Detector-in-the-Loop LLM for Adaptive RTL Hardware Trojan Insertion#635730arXiv (All)
• LLM-based Hardware Development with Hierarchical IRs and End-to-End Multi-Agent Workflow#808723arXiv (OAI Expanded)
• LLM-based Hardware Development with Hierarchical IRs and End-to-End Multi-Agent Workflow#818715arXiv (All)
• Implementación de red celular GSM con hardware SDR.#1004251Repositorio Institucional de la UNSAM
• SparrowSNN: A Hardware/software Co-design for Energy Efficient ECG Classification#152990arXiv (OAI)
• Hardware Synthesis of Synchronous Data Flow Models#640219BYU ScholarsArchive
• HBQ: Hierarchical Scaling Block Quantization with Hardware-Efficiency-Aware Design for Accurate LLM Inference#809901arXiv (OAI Expanded)
• HBQ: Hierarchical Scaling Block Quantization with Hardware-Efficiency-Aware Design for Accurate LLM Inference#819897arXiv (All)
• RunSoC 2.0: Scheduling and Allocating Automotive Software Tasks to Hardware Partitions in Heterogeneous MPSoCs#822055arXiv (All)
• Online Electrical and Hardware Website#73283PhilArchive
• Hardware-Aware FP4 FlashAttention-4#926945arXiv (All)