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Replay Pruning and Few-Bit Integer Inference for Hardware-Efficient Speed-Sign Recognition
Speed-limit sign recognition on an automotive camera system-on-chip (SoC) must fit a detector and a classifier (the reader) into the memory, arithmetic, and energy budgets of the device. In our two-stage recognizer, the detector, a YOLO-family network with ReLU and hard-sigmoid operators, is compres
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