AnalogScout: Simulation-Efficient PVT-Aware Analog Sizing with LLM Agents

arXiv:2610.37319v1 [cs.AR] 27 Oct 2026

AnalogScout: Simulation-Efficient PVT-Aware Analog Sizing with LLM Agents Yichen Long

Keren Zhu*

College of Integrated Circuits and Micro-Nano Electronics Fudan University Shanghai, China longyc26@m.fudan.edu.cn

College of Integrated Circuits and Micro-Nano Electronics Fudan University Shanghai, China krzhu@fudan.edu.cn

Abstract—Analog device sizing must satisfy all specifications across process, voltage, and temperature (PVT) corners to ensure tape-out success, but simulating every candidate at all corners dominates the sizing time and slows design iteration. Conventional surrogate-based optimizers search the sizing space directly, while recent large language model (LLM) agents add circuit knowledge to designs but still delegate the sizes to global optimizers. Both learn the circuit response from repeated multicorner SPICE simulations and optimize on top of it, which becomes expensive under a limited simulation budget. Providing an agent with reusable verified designs and sizing sub-blocks analytically could save most of this budget. We propose AnalogScout, a simulation-efficient PVT-aware sizing framework driven by an LLM agent. Combining elite-design reuse, analytic gm/Id local sizing and global refinement under full-corner verification, AnalogScout reduces power by 43.3% relative to the evolution strategy CMA-ES at an equal budget of 16k simulations on three SKY130 OTAs of increasing complexity, and reaches the final CMA-ES power after 7.0% of that budget. It also attains lower power than Bayesian optimization on all three OTAs and than two re-implemented LLM-driven flows on the two OTAs where they were tested. Index Terms—analog sizing, PVT robustness, simulation budget, LLM agents, gm/Id methodology

I. I NTRODUCTION Analog design automation lags far behind its digital counterpart, and device sizing remains its most labor-intensive step [1]. Sizing selects the widths, lengths and bias currents that meet gain, bandwidth, stability and noise targets at minimum power. In advanced nodes these targets must hold at every process, voltage and temperature (PVT) corner, so each candidate costs a full multi-corner SPICE sweep. PVT-aware sizing searches for device sizes that satisfy all specifications at all corners, mainly through surrogatebased and population-based optimization. Surrogate methods such as Bayesian optimization (BO) fit the corner-dependent response [2]–[4], whereas evolutionary and reinforcementlearning methods [5]–[7] search the design space corner by corner [8], [9]. Both learn the response from sampled simulations, so their cost scales with corners times iterations (Sec. II). LLM agents [10], [11] add circuit knowledge to this search but spend the simulation budget poorly (Fig. 1). LLM-only * Corresponding author: Keren Zhu (krzhu@fudan.edu.cn). This work has been submitted to the IEEE for possible publication. Copyright may be transferred without notice, after which this version may no longer be accessible.

Fig. 1. (i) In the analog design loop, a topology chosen for the specification is sized and verified at all PVT corners until every specification holds; the sizing step (highlighted) consumes most simulations. (ii) Qualitative positions of sizing methods: LLM-only sizing consumes fewer simulations; a global optimizer, alone or driven by an LLM, sizes well with many simulations. AnalogScout targets both quality and efficiency.

sizing loops oscillate between solutions [12], and most agentic flows delegate every device size to a global optimizer [13]– [16]. We further observe that agents re-submit identical designs, restart instead of refining verified ones, and lose most of the budget to simulation-driven local optimizers. An agent that reuses verified designs and sizes sub-blocks analytically would instead spend its budget on improving designs. Inspired by agentic exploration in digital RTL design [17], we propose AnalogScout, a simulation-efficient PVT-aware sizing framework, with three contributions: • Budget-aware exploration: an elite pool and an exact evaluation cache let the agent refine verified designs instead of repeating or restarting them. • Low-simulation local sizing: the agent states gm/Id goals for sub-blocks, which a lookup-table solver resolves with at most three operating-point simulations per block. • Results: on three SKY130 OTAs verified at nine corners, AnalogScout reduces power by 43.3% relative to CMAES at an equal 16k-simulation budget, matches the final CMA-ES power after 7.0% of that budget, and on the Miller and NMC OTAs beats CMA-ES with twice the budget. Section II formulates PVT-aware sizing and reviews existing optimizers, Section III details the four phases of AnalogScout, Section IV compares it with optimizer and LLM baselines and traces where the budget goes, and Section V concludes.

Phase-Explore / Phase-Localize: Agent Loop

Sizing Intent

Edits

LLM Agent Evaluate Edit and Evaluate Device Data and Building Blocks Diagnostics

Agent

Deterministic Flow

Fixed Evaluator Evaluation Cache Exact-Match Reuse

Design Source Topology and Block Choices gm/Id Sizing Intent

Top Designs

Compilation Isolated Execution gm/Id Local Sizing Analytic Solve (Phase-Localize) Design Rule Check

Tool

Simulation

Phase-Restructure: Structure Sweep Recognize Mirrors / Pairs / Compensation Swap Within Family Local Re-Size Phase-Refine: Global Refinement Matched-Group Search Around Best Design Restart on Stagnation

Bias / Start-Up Check Elites and Lessons Elite Pool Elite-Biased Run Starts Lessons

Saturation Check Verified Designs

Sign-Off TT Mismatch Monte Carlo All-Corner Saturation Independent Re-Measurement

Nominal Spec Check Full-PVT Check

Fig. 2. AnalogScout workflow. The LLM agent edits the design source and states gm/Id sizing intent; the fixed evaluator reuses cached results, resolves the intent analytically and checks each design up to full PVT; the top designs then pass through Phase-Restructure, Phase-Refine and sign-off.

II. P RELIMINARIES PVT-aware sizing. Given a topology with device sizes x, PVT-aware sizing solves min Ptt (x) x

s.t.

fi (x, c) meets si

∀i, ∀c ∈ C,

(1)

where Ptt is the power at the typical corner, fi are measured performances such as gain and phase margin, si their specifications, and C the set of process, voltage and temperature corners. Each candidate is therefore evaluated by |C| sets of SPICE simulations, and we measure every method by the number of simulations it consumes. PVT-aware optimizers. Surrogate-based methods fit a model of the corner-dependent response and optimize it, for example a Bayesian neural network shared across corners [4] or a contextual Gaussian process over design and PVT variables [18]. Population-based methods evolve designs per corner and share knowledge across corners [8], and reinforcement-learning methods train one policy over all corners [9], [19]. To reduce the corners simulated, these methods simulate only the current worst corners [20] or cluster similar corners [9], [19]. III. A NALOG S COUT AnalogScout is a simulation-efficient PVT-aware sizing framework in which an LLM agent decides where and toward which goal to size, while deterministic tools compute the sizes and verify the design (Fig. 2). Its input is a topology with starting sizes, the specifications, a PDK and a simulation budget; it seeks a netlist that meets every specification at every PVT corner with low typical-corner power. In Phase-Explore the agent rewrites the netlist, starting from the best verified designs so far; in Phase-Localize it attaches gm/Id goals to sub-blocks, which a lookup-table solver resolves. Phase-Restructure then swaps standard sub-circuits within their family, and PhaseRefine spends the remaining budget on a global search around the best design before sign-off. A. Design Representation and Verification A design is a Python netlist built from PDK MOSFETs, bounded R and C, verified building blocks and precomputed

gm/Id tables [21]–[23]. A fixed evaluator, which the agent cannot modify, solves the DC operating point and checks saturation and the specifications at the typical corner; a design that passes is verified at nine PVT corners (tt; ss, sf and fs at −10% and ff at +10% VDD , each at −40/125◦ C) with fixed testbenches for every specification of Fig. 4. A design is feasible if every specification holds at every corner. Its violation is X V = max max(0, gi,c /qi ) , (2) i

c

where gi,c is the shortfall of specification i at corner c and qi its scale (a log ratio, 10 dB or 30◦ ). Designs are ranked by (infeasible, V , tt power, −margin, area). The agent sees each failing specification at its worst corner and flagged devices. B. Phase-Explore: Agent with Elite Pool A tool-calling LLM agent [24], [25] improves verified designs instead of restarting: it edits the netlist, evaluates it, and queries the gm/Id tables. Each run ends with a lessonslearned summary for later prompts. An elite pool keeps the K = 3 best feasible designs. A new run starts from elite j with probability pj ∝ exp(−(rj − r∗ )/σr ), where rj is its log-power, r∗ the best and σr the spread. Most runs start from an elite, because local rewrites of a feasible design pay off far more often than fresh starts: after two fresh runs, run k of N starts fresh with probability max(0.05, 0.15(1 − k/N )). In development, 15.5% of the agent’s evaluation requests repeated the source text of an earlier design exactly. An exact cache therefore returns the stored result of an identical source instead of simulating it again. C. Phase-Localize: Source-Local Sizing Intent Instead of tuning sizes by simulation, the agent tags a netlist block with @sized and states its goal as an intent tuple
I = B, min IB , [γmin , γmax ], [Lmin , Lmax ], gm,min , (3) where B is a set of devices, IB their current and γ the gm/Id ratio (Fig. 3). Analytic solver. One operating-point simulation of the whole circuit gives each targeted device its actual VDS and

Specification

Sizing Intent Written by the Agent @sized(method="gmid", targets={pair: gm/Id 12-18, L 0.5-1, g_m >= 50 uS}) V DD

CC

vin-

2 pF Minimum Gain (dB) GBW (MHz) PM (deg) SR (V/µs) CMRR (dB) PSRR (dB) Swing (V) Maximum Settling (ns) Noise (µV rms) Area (µm2) Power (µW)

vout

vin+ CL

One Operating-Point Simulation Actual I D, V DS, V SB

gm/Id LUT

Full-PVT Check

Netlist

Minimum Current Meeting gm Floor

3-Stage NMC

2 pF

50 pF

70 10 60 10 60 55 1

58 20 60 10 60 55 0.9

115 5 70 4.5 50 40 1.3

200 65 5000 600

200 85 5000 550

170 26 18000 3300

IV. E XPERIMENTS

W, nf Finger-Width Correction

VSB , so the tables are read at the bias the block really sees. For a stated gm/Id range [γmin , γmax ], a length range and a floor gm,min , the minimum current meeting the floor is ID = max(Imin , gm,min /γ) ,

Folded Cascode

Fig. 4. Benchmark OTAs and their specifications; every specification must hold at all nine PVT corners, TT power is minimized, and the GF180 variants scale voltage specifications by 3.3/1.8.

Fig. 3. Phase-Localize on the two-stage OTA: one operating-point simulation measures the actual bias of each @sized block, the gm/Id table gives the minimum current that meets the gm floor, and the resulting W and nf are written back before full-PVT verification.

γ = γmax ,

Miller 2-Stage

(4)

with L the characterized length nearest the current one. The total width follows from the tabulated current density, Wtot = ID /J(γ, L, VDS , VSB , Wf ), iterated to a fixed point because the density of a binned PDK depends on the finger width Wf = Wtot /nf for nf fingers. Matched devices receive the most conservative common geometry. The solver then re-measures the bias, using at most three operating-point simulations per block. If no legal geometry exists, it reports the limiting constraint and the parameter to relax; the evaluator remains the only authority on feasibility. Why analytic. Every analog candidate needs multi-corner simulation, so a simulation-driven local optimizer competes with the agent for the same budget (Sec. IV-C); precomputed device characterization removes that competition. Stage. Phase-Localize restarts agent runs from the three best Phase-Explore designs; every evaluated design must call an @sized block placed and targeted by the agent. D. Phase-Restructure and Phase-Refine Phase-Restructure recognizes standard structures in the agent’s netlist and swaps each one for another member of its family, for example a wide-swing mirror or Miller-C with a nulling resistor. Phase-Refine refines the best design with CMA-ES [26] over matched device groups, within a factor of 4 of its sizes, with restarts on stagnation. The same engine run from the initial design is the CMA-ES baseline. Sign-off. A design is signed off when it passes full PVT, is saturated at all corners with at least 50 mV margin, reaches a typical-corner mismatch [27] Monte Carlo yield of at least 95% (N = 500), and independent reference scripts reproduce its measurements.

A. Setup Benchmarks. We size three single-ended OTAs of increasing complexity in SKY130 [28] at VDD = 1.8 V, starting from gm/Id hand designs (Fig. 4); the Miller OTA is repeated in GF180MCU [29] at 3.3 V as a test-only PDK. Budget and seeds. Every method receives 16k simulations, where one simulation is one SPICE run of one testbench at one corner in ngspice [30], and only evaluations completed within the budget count. AnalogScout allots 8k simulations to Phase-Explore (60 agent runs of up to 30 steps on deepseek-flash [25]), 4k to Phase-Localize, 2k to PhaseRestructure and the remainder to Phase-Refine. We fixed the method and three hypotheses on development seeds 1–3 and report confirmation seeds 4–8, five per OTA and three for GF180. Baselines. Global CMA-ES [26] and BO [31], [32] size all devices from the starting design with the same bound handling and restarts as Phase-Refine, and CMA-ES is also run with twice the budget. LAS-style [16] and ACP-style [13] baselines let the LLM propose a design and hand its sizes to a global optimizer on the same evaluator. H1 tests AnalogScout against CMA-ES at equal budget, H2 Phase-Localize against an equalbudget restart from the same designs, and H3 Phase-Explore with and without the elite pool; all are one-sided and Holmcorrected at α = 0.05. B. Budget Efficiency At the same 16k-simulation budget, AnalogScout reaches the lowest power of all methods on every OTA (Table I). It reduces power by 43.3% relative to CMA-ES (H1, Holmadjusted p = 9.16 × 10−6 ), and on every OTA each of its five searches beats each CMA-ES search. On the Miller and NMC OTAs, it still reaches 42.4% and 39.0% lower power than CMA-ES with 32k simulations. The convergence curves in Fig. 5 show that AnalogScout matches the final CMA-ES power after 694–1,124 simulations, about 7.0% of the budget. C. Where the Budget Goes The ablation in Table I traces this efficiency to reusing verified designs. With the elite pool, Phase-Explore reaches 18.1% lower power than with fresh starts only at 8k simulations (H3, p = 0.00022). On development seeds, Phase-Localize spends

TABLE I Best full-PVT-feasible TT power of each method at an equal budget of 16k simulations (a) and of AnalogScout’s phases (b). Miller 2-Stage

Folded Cascode

3-Stage NMC

Median P (µW)

Mean ± sample std (µW)

Median P (µW)

Mean ± sample std (µW)

Median P (µW)

Mean ± sample std (µW)

(a) Same-budget comparison Start CMA-ES@16k BO@16k LAS-Style ACP-Style CMA-ES@32k (2x budget) AnalogScout (16k)

451 124 142 99.3 145 107 61.4

451 131 ± 16 140 ± 15 98.8 ± 6.0 147 ± 6 109 ± 6 65.6 ± 14.4

414 163 172 115 168 – 98.1

414 164 ± 10 172 ± 4 118 ± 7 169 ± 7 – 99.9 ± 3.4

2,809 1,561 1,955 – – 1,549 944

2,809 1,554 ± 164 1,965 ± 103 – – 1,559 ± 53 968 ± 111

(b) Ablation Phase-Explore w/o elite pool (8k) Phase-Explore (8k) + Phase-Localize (12k) Phase-Explore + restart (12k) + Phase-Restructure (14k) + Phase-Refine (16k)

98.0 78.0 62.9 64.6 62.9 61.4

102 ± 8 77.5 ± 8.0 66.7 ± 13.9 68.4 ± 12.8 66.5 ± 14.1 65.6 ± 14.4

125 105 98.1 96.9 98.1 98.1

124 ± 4 106 ± 5 100 ± 3 99.3 ± 7.0 100 ± 3 99.9 ± 3.4

– 1,079 953 862 953 944

– 1,054 ± 111 976 ± 116 876 ± 164 976 ± 116 968 ± 111

Configuration

Every reported design meets all specifications of Fig. 4 at all nine PVT corners in the fixed evaluator; P : TT power; n = 5 searches per method (BO, LAS-Style, ACP-Style, CMA-ES@32k: n = 3; Start: one hand design). The NMC CMA-ES@32k entry was added after H1–H3 were fixed and is descriptive only (seeds 4–6; all outcomes reported).

only 4.3% of its simulations on sizing, against 85.3–96.3% for a simulation-based local optimizer, and evaluates about twelve times more designs within the same 4k simulations. At equal budget, however, it shows no significant power reduction over restarting from the same designs (H2, p = 0.645), so we claim its low simulation use, not a power gain. Phase-Restructure leaves the median power unchanged, and Phase-Refine lowers it by at most a further 2.4%. D. Generalization and Sign-off

200

ACKNOWLEDGMENT AI coding assistants (ChatGPT) helped implement the software; the authors reviewed it and take full responsibility for its content.

Refine

3-Stage NMC 2000

50 8

AnalogScout sizes analog circuits across PVT corners budget-efficiently by refining verified designs and resolving local sizing intent with almost no simulations. Future work will resize blocks analytically after structural changes and check saturation at all corners inside the loop; the code and openPDK data will be released.

200

100 0

V. C ONCLUSION

Folded Cascode Restructure

Localize

Miller 2-Stage

500

Explore

Best Feasible Power (µW)

AnalogScout’s designs pass independent all-corner remeasurement about as often as CMA-ES’s. Independent scripts re-measure 156 reference cases from all methods; 46 fail. Per method, 29 of AnalogScout’s 111 cases fail, as do 3 of CMAES’s 12, 2 of BO’s 11 and 14 of the LLM baselines’ 31 (shared cases count for each). Forty of the failures only miss the 50 mV all-corner saturation margin, which the loop checks at the typical corner only; the other 6 exceed a specification by at most 0.5%. Among the best designs, which also undergo typical-corner mismatch Monte Carlo (N = 500), the SKY130 Miller design is signed off, the folded-cascode design fails the re-measurement and reaches a 91.4% Monte Carlo yield (target 95%), and the NMC design misses the 170 ns settling specification by 0.15% at one corner. On GF180MCU, AnalogScout

reduces Miller OTA power by 59.6% versus CMA-ES, and its best design is signed off with a 99.8% Monte Carlo yield. Limitations. Phase-Localize shows no significant power reduction over an equal-budget restart, Phase-Restructure adds little, and the GF180 test covers only the Miller OTA.

16

100

1000 0

8 Simulations (k)

16

0

AnalogScout

8 CMA-ES@16k

16 BO

Fig. 5. Median best full-PVT-feasible TT power of AnalogScout, CMA-ES and BO versus simulations over five confirmation searches (BO: three); thin lines: individual searches; dashed lines: AnalogScout phase boundaries.

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