DiffPower: GPU-Accelerated Differentiable Switching Power Analysis and Optimization

DiffPower: GPU-Accelerated Differentiable Switching Power Analysis and Optimization

I. I NTRODUCTION The cessation of Dennard scaling has elevated power efficiency to a primary design objective in modern integrated circuits (ICs) [1]. In the regime of dark silicon, excessive switching power exacerbates thermal management challenges, constrains the battery life of mobile and edge devices, and imposes severe limits on achievable performance. As a result, Electronic Design Automation (EDA) flows must prioritize power optimization throughout the design hierarchy, from high-level synthesis to placement and routing. However, optimizing for switching power introduces a persistent challenge: the “Analysis-Optimization Gap.” Precise switching power analysis requires estimating the Toggle Rate (TR) of every net, as dynamic power scales with switching activity and capacitive load. The industry standard methodology involves vector-based simulations (e.g., VCD analysis) using commercial tools such as Synopsys Fusion Compiler or PrimePower. While this approach captures temporal correlations to yield high fidelity, its computational latency, which often spans hours or days for multi-million-gate designs, renders it infeasible for integration within a tight, iterative optimization loop. In practice, iterative optimization demands fast approximate models that preserve correct sensitivity rankings rather than exact absolute values. A power model invoked thousands of times per optimization pass need only point the optimizer in the right direction for each step to be productive. This speed-fidelity tradeoff is well-established across EDA, from analytical placers to fast timing estimators. Traditionally, to bridge this gap without resorting to full simulation, designers frequently rely on Static Probability (SP) propagation methods to analytically estimate switching activity. Despite significantly reduced runtimes, traditional SP methods suffer from three fundamental limitations that severely hinder their adoption in advanced optimization flows: 1) Latency Bottlenecks: Serial, level-by-level graph traversal on CPUs remains a throughput bottleneck for multi-million-pin designs, preventing the rapid re-analysis necessary after each incremental netlist change.

2) Sensitivity Blindness: While traditional probabilistic methods effectively identify where power is consumed, they fail to reveal how to optimize it. Without the mathematical sensitivity (∇P , the gradient of total power with respect to local activity), these tools force downstream optimization engines to abandon global mathematical convergence in favor of greedy, localized heuristics. 3) Library and PDK Dependence: Conventional implementations require per-gate-type code for both SP evaluation and, critically, derivative computation. Supporting a new cell library means implementing forward and backward rules for each unique cell function, making gradient-enabled tools inflexible and expensive to extend across technology generations. General-purpose approaches such as BDD-based propagation avoid this but scale poorly to GPU execution. To overcome these barriers, we present DiffPower, a high-speed, fully differentiable approximation engine engineered specifically for inner-loop power optimization. Rather than replacing sign-off-level vector simulation, DiffPower provides rapid gradient-guided feedback between commercial tool runs, enabling optimization decisions at scales where traditional methods are infeasible. The advantages are highlighted in Table I. TABLE I: Comparison of power analysis methodologies and their benefits. Analytical SP is fast compared to Commercial Tools but much slower than DiffPower; it is also accurate for SP but not for TR. ✓ = yes, ✗ = no, = partial. Feature High Fidelity Low Latency Sensitivity (∇P ) PDK-Agnostic

Commercial Tools

✓ ✗ ✗ ✗

Analytical SP

# G #G

Abstract—Accurate and scalable switching power analysis remains a critical bottleneck in modern physical design, often forcing a trade-off between computational speed and modeling fidelity. We present DiffPower, a GPU-accelerated framework for differentiable power analysis and optimization. DiffPower translates design netlists into a PDK-agnostic bytecode representation, enabling analytical gradient computation via reverse-mode automatic differentiation, achieving up to a 1,002× speedup over single-threaded CPU propagation on the largest evaluated design, with the GPU advantage growing with design scale. A hybrid propagation methodology fusing analytical modeling with parallel simulation achieves a median toggle-rate correlation of r=0.96 across ten industrial and benchmark designs. The resulting power gradients, computed up to 904× faster than CPU finite-difference methods with near-perfect rank agreement, enable two downstream applications: (1) gradientweighted cell sizing, which achieves up to 2.98× improvement over localpower heuristics on industrial designs, with even stronger advantages at the 117K-cell scale where competing methods plateau; and (2) power virus generation via gradient ascent, which yields up to 2.13× higher transition-weighted power, replacing a search process that traditionally requires hours.

G #

arXiv:2608.03778v1 [cs.AR] 4 Aug 2026

Isaac Jacobson1 , Zheng Zhao2 , Rashmi Mehrotra2 , Guanglei Zhou1 , Vineet Rashingkar2 , Yiran Chen1 1 Electrical and Computer Engineering, Duke University, Durham, USA 2 Synopsys Inc., Sunnyvale, USA 1 {isaac.jacobson, guanglei.zhou, yiran.chen}@duke.edu 2 {zheng.zhao, rashmi.mehrotra, vineet.rashingkar}@synopsys.com

✗ ✗

DiffPower

✔ ✔ ✔ ✔

Prior approaches have attempted to address these limitations with varying degrees of success. Binary Decision Diagrams (BDDs) support exact probability propagation, but grow exponentially in the worst case and do not map well to data-parallel GPU execution [2]. Recent GPU-accelerated differentiable EDA frameworks have demonstrated the power of combining hardware parallelism with automatic differentiation: INSTA [3] enables differentiable static timing analysis on a levelized graph, while additional differentiable timing optimizers [4], [5] target delay and slack. DiffPower extends this paradigm to switching power, where SP propagation constitutes a continuous relaxation of the Boolean circuit [6]. For power estimation specifically, GATSPI [7] accelerates gate-level simulation with bitpacked parallel logic on GPUs but does not provide analytical gradients; GRANNITE [8] infers toggle rates via a graph neural network but also lacks gradient information. We adopt GATSPIstyle bit-packed simulation to derive per-pin scaling factors that calibrate the differentiable model, so that optimization gradients reflect accurate toggle rates. To achieve PDK-agnostic gradient computation, we use stack-

machine bytecode compiled from Boolean expressions. The same bytecode drives both forward SP propagation and reverse-mode gradient computation. This follows the principle of differentiating an intermediate representation, directly analogous to compiler-level Automatic Differentiation (AD) systems such as Enzyme [9]. Compiling to bytecode has precedent in simulation (Icarus Verilog VVP [10]). DiffPower extends the idea to massively parallel GPU execution, where the zero-address format minimizes warp divergence. To demonstrate the practical value of power gradients, we apply DiffPower to two downstream tasks where global sensitivity information is critical but currently unavailable: power-aware cell sizing and power virus generation. Gate sizing is a well-studied NPhard problem [11]; most prior work focuses on timing rather than power [12]–[15]. Differentiable methods have also been applied to physical design, such as placement [16] and routing [17]. Power virus generation seeks to induce near-worst-case switching power in order to stress-test a circuit. Existing state-of-the-art methods rely on evolutionary search [18]–[22], gate-level cost-benefit heuristics [23], or greedy discrete search, all of which scale poorly to large designs. In the broader field of automatic test pattern generation, DEFT [24] applies differentiable programming to fault detection; DiffPower takes a similar approach to generate power viruses across designs. Concretely, DiffPower maps the netlist to a levelized pin-level Directed Acyclic Graph (DAG) processed by custom CUDA kernels, enabling end-to-end differentiable power analysis with exact gradients in a single backward pass. It overcomes latency through GPU parallelism, provides sensitivity through automatic differentiation, and achieves library independence through a bytecode abstraction. Our contributions are as follows: • We present DiffPower, the first GPU-accelerated, fully differentiable switching power analysis framework that achieves up to 1,002× speedup over CPU propagation, completing forward and backward passes on a 652K-cell design in under 30 ms each. • We propose a PDK-agnostic bytecode representation that compiles arbitrary Boolean cell functions into stack-machine instructions, enabling exact gradient computation for any cell library without gate-specific derivative code. • We introduce a hybrid propagation methodology that bridges bit-packed simulation with a differentiable model, achieving a median TR correlation of r=0.96 with an SP r > 0.96 on ten of ten industrial and benchmark designs. • We demonstrate gradient-guided cell sizing that achieves 2.98× improvement over local-power heuristics on an industrial design. • We formulate a highly efficient, gradient-ascent-based power virus generation technique that consistently outperforms evolutionary searches, achieving up to 2.13× higher transitionweighted power. II. P RELIMINARIES A. Switching Power Model The dynamic switching power (Psw ) of a digital CMOS circuit is formally modeled as the sum of power dissipated by charging and discharging capacitive loads across all nets in the design: X 1 2 Psw = · Vdd · αi · fclk · Cload,i (1) 2 ∀i∈Nets

where Vdd denotes the supply voltage, fclk represents the clock frequency, Cload,i is the total capacitive load of net i (including wire capacitance and pin capacitance of driven cells), and αi signifies the switching activity (Toggle Rate) of net i. In the context of

physical synthesis optimization, Vdd and fclk are typically fixed system constraints determined by the operating mode. P Therefore, optimization efforts focus on minimizing the sum αi · Cload,i through logic restructuring (affecting αi ) and cell sizing (affecting Cload,i ). B. Temporal Independence Assumption To efficiently compute αi without reliance on explicit input vectors, we employ Static Probability, denoted as P (x = 1) or simply P , which represents the probability that a signal x is at logic ‘1’. Under the assumption of Temporal Independence (where the state of a signal at time t is independent of its state at time t − 1), the toggle rate (TR) is derived solely from the static probability [25]: TRmodel = 2 · P (x = 1) · (1 − P (x = 1))

(2)

This equation models the probability of a transition occurring (0→1 or 1→0) based on the randomness of the data. While this approximation neglects temporal correlations between clock cycles and spatial correlations (e.g., reconvergent fan-out, where the same logical signal reaches a gate along multiple paths and invalidates the independence assumption), it yields a differentiable closed-form expression. This allows us to analytically compute partial derivatives of power with respect to probability. Crucially, for gradient-guided optimization, the model need only rank pins correctly by activity level, not predict absolute toggle rates, for the gradients to point the optimizer in the right direction. Section III incorporates spatial correlations through a bit-packed simulation pass fused with the analytical model, preserving this ranking fidelity across designs with reconvergent structure. C. Power Virus and Transition-Weighted Power A power virus is an input (or state-transition) pattern that induces near-worst-case or worst-case switching power in a design. Power virus generation is important for (i) worst-case power and thermal validation, (ii) stress testing of power delivery and packaging, and (iii) design margin verification. For combinational logic, the problem is: given primary inputs (or combinational startpoints) at two consecutive time steps, choose vectors v0 and v1 so that the resulting transition-weighted power is maximized. Formally, after propagating v0 and v1 through the netlist to obtain logic values at every pin, the transition-weighted power (the quantity we maximize) is X
Pvirus = Cload,i · I vali (v0 ) ̸= vali (v1 ) (3) i∈pins

where vali (v) is the logic value at pin i under input v, and I(·) is the indicator function. This is the same metric used in vectorbased sign-off: it counts capacitance-weighted transitions. The computation of the true power virus is an NP-hard problem. Existing approaches, such as evolutionary search and greedy one-bit flip, rely on discrete evaluations of Pvirus , rendering them computationally intractable for modern million-gate designs. Because greedy search requires O(|S|2 ) evaluations per restart (flipping each of the |S| startpoints and evaluating), combinatorial heuristics completely break down at scale, effectively trapping designers in local optima beyond a few thousand inputs. Evolutionary search scales better but still requires many function evaluations and population management, with runtimes reaching hours on industrial-scale designs. A differentiable approximation enables gradient ascent in the continuous probability space, exploring the |S|-dimensional landscape in O(T · |pins|) time for T gradient steps, orders of magnitude faster than population-based or combinatorial methods.

Bytecode Arrays

Levelized Graph

Design Verilog, SAIF, LIB, SDC

Reference Tool Preprocessing

One-time Commercial Tool Preprocessing

Evaluation Propagation

Bitwise Propagation

Power Virus Vectors

SP Propagation

𝛽 Calibration

Power Virus Generation

Back Propagation

Gradient

Toggle Rates & Switching Power

GPU Accelerated Power Propagation

Optimized Netlist Power-aware Sizing

Power-aware Optimization

Fig. 1: Overview of DiffPower. The framework initializes from a commercial reference tool, builds a levelized pin graph with corresponding bytecode arrays loaded to GPU memory (green box on the left). DiffPower propagates static probability values algebraically to model toggle rates, calibrates them via bitwise simulation (β-calibration), and computes exact gradients through backpropagation (blue box in the middle). These gradients guide cell sizing and power virus generation via gradient ascent (orange box on the right).

III. P ROPAGATION M ETHODOLOGY The core of the DiffPower framework is a GPU-resident graph engine capable of performing both forward evaluation (inference) and backward differentiation (sensitivity analysis). By keeping the entire graph structure in GPU memory, we avoid the high latency of host-todevice data transfer during iterative updates. Fig. 1 shows a high-level overview of the framework. A. Graph Construction and Levelization We use a Tcl extraction script executed within the commercial host environment (e.g., Fusion Compiler) to extract structural connectivity, physical attributes (specifically Cload for every net and pin), and functional definitions of the cells within a design. We then construct a DAG representation of the circuit similar to previous works [3], [6], [24]. Nodes represent individual pins (rather than cells), enabling fine-grained modeling of both intracell and inter-cell arcs. To preserve a DAG structure, the outputs of sequential elements (flip-flops, latches) are treated as pseudo-primary inputs (PPIs) with fixed probability values, while their inputs serve as pseudo-primary outputs (PPOs). Infrastructure nets, such as clock buffers, test-enable lines, and scan logic, are handled identically: they become fixed boundaries with fixed static probabilities, excluded from gradient updates while their downstream load contributions are retained. The analysis is thus confined to the combinational logic clouds between sequential boundaries, following the same scope adopted by prior differentiable gate-level analysis frameworks [3], which contain the majority of optimization opportunities. To maximize GPU parallelism, the graph is levelized: nodes are assigned levels such that a node at level L depends exclusively on nodes at levels < L. All nodes at a given level then execute in a single parallel kernel launch. DiffPower features an automated preprocessing pipeline (Algorithm 1) that translates Boolean expressions into GPU-executable bytecode. A lexer and recursive-descent parser (precedence: NOT > AND > XOR > OR) build an AST, which is compiled in postorder into stack-machine opcodes: IN(k), NOT, AND, OR, XOR, CONST_0/1. The preprocessor deduplicates expressions by bytecode signature and assigns compact logic id indices. Common gate types (AND, OR, NAND, NOR, XOR, BUF, INV) are recognized and routed to hand-optimized CUDA kernels for slightly higher throughput. All remaining cells, regardless of

Algorithm 1 PDK Bytecode Compilation (Preprocessing) 1: Input:

functions.csv with rows (ref name, pin name, f unc str) 2: Output: generated_logic.json — flat bytecode arrays with per-gate metadata 3: ops arr ← [ ]; args arr ← [ ] 4: of f sets ← {}; lengths ← {}; id map ← {} 5: next id ← GEN_START 6: for each unique (ref name, out pin) logic key k do 7: f unc str ← lookup from functions.csv // Tokenize: IDENT, AND, OR, XOR, NOT, PAREN, CONST 8: tokens ← L EXER(f unc str) // Parse with precedence: NOT > AND > XOR > OR 9: ast ← R ECURSIVE D ESCENT PARSER(tokens) 10: input order ← C OLLECT I NPUT O RDER(ast) 11: sym idx ← {name 7→ i : (i, name) ∈ enumerate(input order)} // Post-order; ops: IN, NOT, AND, OR, XOR, CONST 12: bc ← ASTT O B YTECODE(ast, sym idx) // Check if bytecode matches a known common gate 13: known ← M ATCH K NOWN G ATE(bc, input order) 14: if known ̸= None then 15: id map[k] ← known ▷ Use hardcoded gate ID 16: else 17: of f sets[k] ← |ops arr|; lengths[k] ← |bc| 18: ops arr.extend([op for (op, ) ∈ bc]) 19: args arr.extend([arg for ( , arg) ∈ bc]) 20: id map[k] ← next id; next id += 1 21: end if 22: end for 23: Export {id map, ops arr, args arr, of f sets, lengths} complexity, are handled by the general bytecode interpreter, which requires no gate-specific code. Because all threads at a given level execute the same interpreter loop (differing only in their bytecode offset), warp divergence is minimized. This enables the representation to scale to arbitrary PDK cell libraries with O(|V |) complexity per level, where |V | is the number of nodes at that level.

Algorithm 2 GPU Levelized Forward SP Propagation 1: Input: Levelized pin graph G with L levels; CSR adjacency

(indptr, indices); logic id[·], compiled bytecode arrays, input permutation perm[·], startpoint SPs P [·] 2: Output: Propagated SP P [·] and modeled TR α̂[·] for all N pins 3: for ℓ = 0 to L − 1 do ▷ Host launches two kernels per level Kernel 1 — Wire propagation (1 CUDA thread per net-sink at level ℓ): 4: tid ← blockIdx · blockDim + threadIdx 5: i ← netFrontier ℓ [tid ] ▷ Map thread to net-sink pin 6: P [i] ← P [ indices[indptr [i]] ] ▷ Copy driver’s SP to sink Kernel 2 — Cell evaluation (1 CUDA thread per cell-output at level ℓ): 7: i ← cellFrontier ℓ [tid ] ▷ Map thread to cell-output pin 8: Gather ak ← P [ indices[indptr [i]+k] ] for k = 0, . . . , ni −1 9: if logic id[i] < GEN_START then // e.g. AND: a0 · a1 ; NAND: 1 − a0 · a1 10: P [i] ← H AND O PTIMIZED SP(logic id[i], a0 , . . . , ani −1 ) 11: else 12: Permute via perm[i]; run bytecode interpreter 13: P [i] ← clip(stack top, 0, 1) 14: end if 15: end for Kernel 3 — TR estimation (N threads, all pins in parallel): 16: α̂[i] ← 2 · P [i] · (1 − P [i]) for all pins i ▷ Eq. (2) B. Pass 1: Differentiable Forward Propagation DiffPower performs a differentiable algebraic propagation of static probability (detailed in Algorithm 2). The host iterates over levels; at each level two CUDA kernels execute in sequence. Kernel 1 handles wire (net) nodes by copying the driver’s SP to every sink. Kernel 2 handles cell-output nodes: each thread gathers predecessor SPs via Compressed Sparse Row (CSR) indexing and dispatches to either a hand-optimized SP formula (common gates) or the general bytecode stack-machine interpreter (arbitrary cells) based on logic id. A final kernel estimates TRmodel from the temporal-independence assumption (Eq. (2)). All SP operations are differentiable, enabling exact gradient computation in the backward pass (Section III-E). The complete forward pass runs in O(|E|) time, where |E| is the number of edges in the pin graph, and total switching power is computed by Eqs. (1) and (2). C. Pass 2: Bit-Packed Parallel Simulation The temporal independence model misses spatial correlations (e.g., reconvergent fan-out). To capture these, we implement a bit-packed parallel simulation pass inspired by GATSPI [7], computing per-pin TRacc values that are fused with the analytical estimates in the hybrid step (Section III-D). 64-bit input vectors are generated via Markov chains calibrated to target SP and TR values. Startpoints sharing an upstream sequential driver receive the same bitstream to preserve correlations. The accurate toggle rate is computed as: 1 X TRacc = PopCount(vect ⊕ vect−1 ) (4) Nsim cycles

D. Hybrid Methodology Passes 1 and 2 are fused into a single hybrid propagation pipeline. For each pin, the ratio of the simulated toggle rate to the analytical estimate defines a per-pin scaling factor βi :   TRacc,i , βmin , βmax (5) βi = clip TRmodel,i

Clipping bounds prevent gradient suppression or explosion. The clipped βi scales the forward activity values reported as Hybrid in Section V and, during backpropagation, the analytical gradient, so that both reflect spatial correlations captured by the simulation pass: ∂Ptotal ∂Ptotal ← βi · (6) ∂Pi ∂Pi This per-pin scaling is analogous to the Straight-Through Estimator (STE) used in quantized neural networks [26] and in EDA for learning-driven gate sizing [15]. Biased gradient estimators can still converge in non-convex settings under mild conditions [27], and dynamic scaling prevents vanishing gradients [28]. The simplicity of this estimator is intentional: βi requires no learned parameters and adds only a single element-wise multiply during backpropagation. The core contribution is the end-to-end hybrid pipeline that produces simulation-informed analytical gradients at GPU speed, a capability no prior power analysis tool provides. E. Gradient Backpropagation DiffPower computes exact power gradients by traversing the levelized graph in reverse topological order (analogous to backpropagation in neural networks [3], [4]). For each node i, the gradient of total switching power with respect to its SP is accumulated from downstream nodes and a local power term: X ∂Ptotal ∂Plocal ∂Pj ∇i = = + (7) ∇j · ∂Pi ∂Pi ∂Pi j∈fanout(i)

The local term follows from differentiating the temporalindependence model (Eq. (2)): ∂Psw /∂Pi ∝ Ci · (1 − 2Pi ). For common gate types, the partial derivatives ∂Pj /∂Pi are evaluated via hand-optimized backward kernels (e.g., ∂PAND /∂PA = PB for AND(A, B)). For all other cells, DiffPower employs reverse-mode AD directly over the bytecode instruction sequence (Algorithm 3). During the forward pass, operands of each binary operation are recorded into a per-gate tape. The backward pass traverses bytecode in reverse, applying chain-rule derivatives: • AND(a, b): ∂(ab)/∂a = b, ∂(ab)/∂b = a • OR(a, b) = 1 − (1 − a)(1 − b): ∂/∂a = 1 − b, ∂/∂b = 1 − a • XOR(a, b) = a + b − 2ab: ∂/∂a = 1 − 2b, ∂/∂b = 1 − 2a • NOT(x) = 1 − x: passes gradient with sign flip (−1) IN(k) accumulates its gradient into the predecessor pin via atomic addition. This yields exact gradients for arbitrary PDK cells with no gate-specific code; the backward pass has the same O(|E|) complexity as the forward pass. Gradient correctness is verified against finite-difference estimates both on sampled root pins and via exhaustive per-pin sweeps (Section V-C). IV. G RADIENT-BASED O PTIMIZATION F RAMEWORKS The backward pass of Section III yields what we term power gradients: the derivatives ∂Ptotal /∂Psw,i of total switching power with respect to each pin’s activity. These are obtained from the SP gradients ∂Ptotal /∂Pi computed in Section III-E via the chain rule through Eq. (2). Unlike local metrics that consider only a cell’s own power consumption, power gradients capture downstream effects, revealing how a change at one pin propagates through fanout and affects power throughout the design. This global sensitivity information is unavailable to conventional power analysis tools and can, in principle, inform any power-aware optimization that benefits from knowing how local activity changes propagate globally. We demonstrate this with two representative applications: gradient-ascent power virus generation and gradient-weighted cell sizing for power reduction.

Algorithm 3 Bytecode Backward Pass (Reverse-Mode AD)

Algorithm 4 DiffPower Gradient-Ascent Power Virus Search

1: Input: Bytecode bc of length L; forward tape tape a [0..L−1],

1: Input: Graph G, startpoints S, steps T , rate η, optional β-scaling 2: Output: Vectors v0 , v1 maximizing Pvirus 3: Notation: Pi = SP at startpoint i; ∇i = ∂Ptotal /∂Pi 4: Initialize Pi ← 0.5 for all i ∈ S 5: if β-scaling enabled then

tape b [0..L−1]; upstream gradient gout ; number of gate inputs n 2: Output: Per-input gradients ∇in [0..n−1] 3: ∇in [i] ← 0 for i ∈ [0, n) 4: Initialize backward grad-stack: gstk ← [gout ] 5: for i ← L − 1 downto 0 do 6: op, arg ← bc[i] 7: if op = IN then 8: g ← gstk .pop() 9: ∇in [arg] += g 10: else if op = NOT then 11: g ← gstk .pop() 12: gstk .push(−g) ▷ ∂(1 − x)/∂x = −1 13: else if op = AND then 14: g ← gstk .pop(); a ← tape a [i]; b ← tape b [i] 15: gstk .push(g · b) ▷ ∂(ab)/∂a = b 16: gstk .push(g · a) ▷ ∂(ab)/∂b = a 17: else if op = OR then 18: g ← gstk .pop(); a ← tape a [i]; b ← tape b [i] 19: gstk .push(g · (1 − b)) ▷ ∂/∂a = 1−b 20: gstk .push(g · (1 − a)) ▷ ∂/∂b = 1−a 21: else if op = XOR then 22: g ← gstk .pop(); a ← tape a [i]; b ← tape b [i] 23: gstk .push(g · (1 − 2b)) ▷ ∂/∂a = 1−2b 24: gstk .push(g · (1 − 2a)) ▷ ∂/∂b = 1−2a 25: else if op ∈ {CONST_0, CONST_1} then 26: gstk .pop() ▷ Constants have no input dependence 27: end if 28: end for A. Gradient-Weighted Timing-Aware Cell Sizing Cell sizing is inherently a discrete optimization problem in which the designer selects among library-specific alternatives (e.g., AND2 X1, AND2 X2, AND2 X4) that trade off drive strength (and hence capacitance) against timing margin. Standard approaches rank cells by local capacitance or slack; we introduce a gradient-weighted ranking metric that combines global sensitivity with local power to maximize the power reduction achieved per cell resized. We observe that the most effective downsizing candidates exhibit both high sensitivity (where a small local change produces a large global power reduction) and high existing local power consumption. Formally, we define the ranking score Si for cell instance i as: Si =

∂Ptotal × Psw,i ∂Psw,i

(8)

The gradient term |∂Ptotal /∂Psw,i | captures the global impact of modifying cell i: downsizing a cell that drives a high-fan-out net yields a large gradient because the capacitance change propagates to many downstream pins, each contributing to total power. The local power term Psw,i ensures that the metric focuses on cells where there is substantial switching activity to reduce. A cell with a large gradient but near-zero activity offers no practical savings. The product acts as a first-order estimate of the achievable power reduction from resizing cell i, analogous to the gain metric used in timing-driven sizers [13], [14] but targeting switching power rather than delay. The sizing procedure operates iteratively. At each iteration, cells not on a critical timing path are ranked by Si in descending order. For the top-ranked cell, all library-specific legal substitutions are identified using the get_alternative_lib_cells command in the commercial environment. Each candidate is evaluated: the sub-

// One-time bit-packed simulation for spatial correlations 6: Compute βj ← TRacc,j /TRmodel,j per pin j 7: Store β for use in backpropagation 8: end if 9: for t = 1 to T do

// Map startpoint SPs to full pin array, propagate, backprop 10: a ← B UILD SPA RRAY(P1 , . . . , P|S| ) 11: F ORWARD P ROPAGATION GPU(G, a) 12: ∇ ← BACKWARD P ROP T OTAL P OWER(G) 13: for each startpoint i ∈ S do 14: Pi ← Pi + η · ∇i 15: Pi ← clip(Pi , 0, 1) 16: end for 17: end for

▷ Scaled by β ▷ Ascent step

// Discretize continuous SPs to binary vectors 18: v0,i ← I(Pi ≥ 0.5), v1,i ← 1 − v0,i for all i ∈ S

// Evaluate true Pvirus on discrete vectors via bitwise simulation 19: Pvirus ← E VALUATE P OWER F ROM V ECTORS(G, v0 , v1 ) 20: return v0 , v1 , Pvirus

stitution is accepted if it reduces switching power without creating a timing violation. Slack is queried directly from the commercial timer after each trial substitution, and any candidate introducing negative slack on any path through the cell is rejected, so accepted swaps remain sign-off-consistent. Because the global gradient changes as cells are resized (a phenomenon known as gradient staleness), the ranking score becomes gradually less accurate over successive iterations. In practice, we process cells in small batches and periodically re-invoke DiffPower’s forward and backward passes to refresh the gradient, maintaining ranking fidelity at trivial computational cost. Re-propagation takes ∼27 ms on the small design and ∼33 ms on the medium design, multiple orders of magnitude faster than existing methods. B. Power Virus Generation via Gradient Ascent The true Pvirus objective (Eq. (3)) is discrete and nondifferentiable, counting capacitance-weighted bit-flips. We relax the problem by treating startpoint SPs as continuous variables in [0, 1] and maximizing the differentiable proxy: X Pproxy = Ci · 2 Pi (1 − Pi ) (9) i∈pins

which equals the expected transition probability at each pin under the temporal-independence model. Starting from a uniform initialization (Pi =0.5 for all startpoints), each gradient ascent step computes ∇Pi Pproxy via one forward/backward pass and updates Pi ← clip(Pi + η · ∇i , 0, 1). After T steps (typically T =100), we discretize by thresholding: v0,i =I(Pi ≥ 0.5) and v1,i =1−v0,i , producing an input pair that maximizes transitions at the startpoints. Two deterministic forward passes evaluate the true Pvirus on the discrete vectors. The entire procedure runs in O(T · |pins|) time and requires no population management, fitness evaluation budget, or discrete search heuristics. A one-time bit-packed run can optionally compute β factors to scale gradients during ascent, improving the search direction when the temporal-independence model misestimates toggle rates. Algorithm 4 summarizes the full procedure.

GPU Kernel (s) Design

Alg.

Bitwise Backward

Small 0.0135 0.0124 Medium 0.0161 0.0160 Large 0.0289 0.0269

0.0132 0.0165 0.0242

CPU

Ref.

GPU vs.

(s)

(s)

CPU

0.416 4.09 31× 4.546 14.15 282× 28.96 224.38 1,002×

DiffPower's Static Probability

TABLE II: Propagation runtime on the three proprietary designs. GPU columns are per-pass kernel times; CPU is DiffPower algebraic propagation running on CPU instead; speedup is algebraic vs. algebraic; Ref. is the commercial reference tool. Design sizes: small (13K comb. cells), medium (117K), large (652K).

V. E XPERIMENTAL R ESULTS

1.0 0.8 0.6 0.4 0.2 0.0

A. Experimental Setup

B. Propagation Runtime & Accuracy We evaluate three propagation modes: (1) Modeled algebraic SP propagation under the temporal-independence assumption, (2) Bitwise 64-bit parallel simulation capturing spatial correlations, and (3) Hybrid: the full pipeline fusing analytical SP with per-pin βscaling from bitwise TR. Table II reports GPU kernel execution times, single-threaded CPU DiffPower times, and commercial reference tool times across the three proprietary designs. DiffPower completes forward propagation and backpropagation on a 652K-cell design in under 60 ms, approximately 1,002× faster than single-threaded CPU propagation and three to four orders of magnitude faster than the commercial reference tool. Table III presents per-pin SP and TR correlation against the commercial reference across all ten designs. DiffPower’s hybrid pipeline (100 Monte Carlo iterations, per-pin β-clipping with βmin = 0.1, βmax = 10) achieves a median SP correlation of r=0.988 and median TR correlation of r=0.96 across all ten designs. On the nine well-conditioned designs, SP r ≥ 0.98 and TR r ranges from 0.937 to 0.995, indicating that per-pin activity rankings closely match the commercial reference. For comparison, the analytical-only (Modeled) baseline achieves high SP correlation (median r=0.997) but lower TR correlation (median r=0.86), reflecting the spatial-correlation gap that the bit-packed simulation pass addresses. The large proprietary extraction (652K cells) establishes the current operational boundary, achieving TR r = 0.84, a limit of the combinational-boundary approximation analyzed in Section VI. Figs. 2a and 2b show per-pin SP and TR scatter plots for DiffPower’s hybrid propagation on the small design. SP values maintain tight alignment with the commercial reference (r = 0.993, Fig. 2a),

0.2

0.4

0.6

0.8

Reference Tool's Static Probability

1.0

(a) Hybrid static probability (SP) computed by DiffPower vs. commercial reference for all pins in the small design (r = 0.993).

DiffPower's Toggle Rate

Experiments were conducted on a single NVIDIA A100 GPU (40 GB VRAM) and an AMD EPYC 7F52 16-Core host. The accuracy baseline is commercial switching-activity propagation run through Synopsys Fusion Compiler or Design Compiler. We evaluate DiffPower on ten designs. Three are proprietary combinational netlists implemented in different technology nodes, extracted with Fusion Compiler: a small design with 13K cells, a medium design with 117K cells, and a larger deep-learning accelerator with 652K cells, included deliberately to stress-test the combinational-boundary assumption at scale. The remaining seven are IWLS 2005 open-source benchmarks [29] synthesized with Design Compiler. All comparisons are scoped to combinational switching activity, consistent with prior differentiable gate-level analysis frameworks [3], [24]: sequential elements are treated as analysis boundaries, with their output SP and TR taken from the design database. The commercial reference tool is run with propagate_switching_activity from the same register-output starting conditions, giving a like-for-like comparison of combinational propagation accuracy.

0.0

0.5 0.4 0.3 0.2 0.1 0.0

0.0

0.1

0.2

0.3

0.4

Reference Tool's Toggle Rate

0.5

(b) Hybrid toggle rate (TR) computed by DiffPower vs. commercial reference for all pins in the small design (r = 0.982).

Fig. 2: Per-pin activity correlation between DiffPower and a commercial reference tool on the small design (53K pins). and TR values achieve r = 0.982 (Fig. 2b), confirming that perpin activity rankings closely match the commercial tool and that the resulting power gradients are well-directed for optimization. Table III also shows the memory footprint of each design to store the DAG and propagation value buffers. This scales linearly with pin count, from 35.8 KB on the smallest benchmark to 213.5 MB on the largest design, all fitting comfortably within a single GPU’s VRAM. C. Gradient Validation We validate gradient correctness at two levels: pointwise accuracy and large-scale rank agreement. Pointwise finite-difference validation. For each of 32 randomly sampled root pins, we perturb the root SP by ε = 10−4 and repropagate to obtain a one-sided finite-difference gradient estimate. On five designs (sasc, spi, pci, aes_cipher, medium), all 160 tested pins achieve 100% pass rate with mean relative error below 10−4 and maximum relative error below 2 × 10−4 , confirming that reverse-mode AD through the bytecode interpreter produces exact derivatives of the forward SP model. Extending this validation to full-design scale, we run exhaustive finite-difference sweeps over all root-driven pins for aes_core and pci. The median relative error is 2.71 × 10−4 and 1.50 × 10−4 , respectively; the median is reported because a heavy tail of near-zero gradient magnitudes inflates the relative-error denominator. Top-100/500/1,000 rank overlaps against the brute-force gradients are 100/499/1,000 on aes_core and 99/486/990 on pci, confirming that the analytical backward pass

TABLE III: Propagation accuracy of the analytical (Modeled) and full-pipeline (Hybrid) methods against the commercial reference tool. Hybrid results use 100-iteration Monte Carlo + per-pin β-scaling. Designs in the upper group are proprietary; the lower group is opensource benchmarks. Memory footprint is the amount of GPU memory used to store the graph and buffers used in propagation. Modeled

Hybrid

Cells

Levels

Memory Usage

SP r

TR r

SP r

TR r

Proprietary designs small testcase 53K medium testcase 453K large testcase 2.6M

13K 117K 652K

70 84 104

3.8 MB 32.8 MB 213.5 MB

0.950 0.921 0.970

0.641 0.715 0.831

0.993 0.981 0.969

0.982 0.937 0.835

IWLS 2005 open-source benchmarks sasc 455 173 spi 1.1K 431 i2c 1.8K 486 4.7K 1.7K aes cipher des 10.4K 3K pci 33.4K 8.7K aes core 46K 13K

23 18 56 13 60 50 52

35.8 KB 90.0 KB 138 KB 362 KB 823 KB 2.4 MB 3.7 MB

1.000 0.997 0.999 1.000 0.997 0.998 0.997

0.987 0.992 0.928 0.997 0.817 0.884 0.476

0.999 0.995 0.983 0.998 0.983 0.980 0.994

0.982 0.961 0.949 0.995 0.963 0.954 0.955

reproduces numerical sensitivity rankings almost exactly across entire designs. Gradient rank correlation. Because the downstream applications rely on gradient-ranked pin ordering rather than absolute gradient magnitudes, rank agreement with ground truth is the critical validation metric. To assess whether analytical gradients identify the same high-sensitivity startpoints as brute-force numerical differentiation, we run a large-scale finite-difference sweep on the medium industrial design (117K cells, 50,222 total roots). We evaluate a stratified subset of 15,000 roots, biased toward high-|∇| roots to focus on the optimizer-relevant portion of the distribution. The GPU analytical gradient completes in 68 s (dominated by graph creation overhead followed by one forward/backward pass); the CPU finite-difference sweep (ε=10−4 , one perturbation per root) requires 61,668 s (∼17 hours), a 904× speedup. The two gradient vectors achieve Pearson r≈1.0 and top-k Jaccard = 1.0 for all k ≤ 500, confirming near-perfect gradient agreement at the scale most relevant to production optimization.

Switching Power Reduction (µW)

Pins

Design

1.0 0.8 0.6 0.4 0.2 0.0 0

50

100

150

Number of Cells Sized

200

250

(a) Small design (13K cells). After 250 iterations, DiffPower achieves a reduction of 1.31 µW, outperforming Local Power (0.44 µW) by 2.98× and Random (0.30 µW) by 4.4×.

Switching Power Reduction (µW)

D. Optimization Quality We evaluate the efficacy of DiffPower’s guided cell sizing by comparing the power reduction from iterative cell sizing against existing methodologies. Fig. 3 shows the cumulative power reduction under the iterative cell sizing scheme on the small (a) and medium (b) industrial designs. Three cell-ordering strategies are compared: random selection, local P power ( C · TR), and DiffPower’s power-gradient-weighted metric (|∇Ptotal | × Psw,i ). On the small design, the gradient-weighted metric outperforms local power by 2.98× after 250 cells resized. On the medium design, the advantage is even more pronounced: after 1,500 iterations, DiffPower achieves 200 µW cumulative reduction while random achieves only 30 µW and local power achieves zero. Power gradients capture both local power and global fan-out effects, explaining why the advantage grows with design complexity. Deeper logic cones amplify the value of global sensitivity information: local heuristics that ignore downstream impact plateau, while gradientweighted sizing continues to find productive swaps. These curves (especially Fig. 3b) exhibit flat regions where no power gain is realized; these occur when the top-ranked cell has no legal replacement that improves power without introducing negative slack. The sizer skips such cells and advances to the next candidate, resuming reduction once a viable swap is found. This is especially notable in the local power heuristic, which struggles to identify any timing-feasible downsizing alternatives.

DiffPower Local Power Heuristic Random Baseline

1.2

200

DiffPower Local Power Heuristic Random Baseline

150 100 50 0 0

250

500

750

1000

Number of Cells Sized

1250

1500

(b) Medium design (117K cells). After 1,500 iterations, DiffPower achieves a reduction of 200 µW while Random reaches only 30 µW and Local Power effectively zero

. Fig. 3: Cumulative switching power reduction during iterative cell sizing. Cells are processed in rank order; three P ordering strategies are compared: random selection, local power ( C·TR), and DiffPower’s gradient-weighted metric (|∇Ptotal | × Psw,i ).

TABLE IV: Power virus quality and runtime: gradient ascent vs. evolutionary search. Both methods use the same cap-weighted transition metric Pvirus (Eq. (3)). Gradient ascent uses T =100 forward/backward passes; evolutionary search has a 1-hour budget and population evaluations are done in parallel on our GPU propagation engine. Pvirus Score Design

Cells

Gradient

sasc 173 spi 431 i2c 486 aes cipher 1.7K des 3K pci 8.7K 13K aes core

7.1 49.1 36.9 161.6 248.1 768.5 2,367.2

small medium large

Evol. Gap (%) DiffPower Time 6.7 32.4 28.8 146.4 235.7 481.4 1,110.2

+6 +52 +28 +10 +5 +60 +113

<1 s <1 s <1 s <1 s 2s 5s 16 s

13K 222.7 182.3 117K 2,286.1 1,163.9 6 652K 3.789×10 3.788×106

+22 +96 +0.03

20 s 74 s 615 s

E. Power Virus Generation We compare DiffPower’s gradient-ascent power virus against an evolutionary search baseline on ten designs (seven IWLS benchmarks plus the three industrial designs). Both methods use the same capweighted transition metric Pvirus (Eq. (3)). The gradient method runs T =100 forward and backward passes in O(T ·|pins|) time. Evolutionary search is given a 1-hour wall-clock budget with population fitness evaluations parallelized on DiffPower’s GPU propagation engine, giving the evolutionary baseline every computational advantage. We focus on the evolutionary comparison because it is the only baseline that scales to large designs; greedy one-bit flip (O(|S|2 ) per restart) is intractable for designs with even thousands of cells. Table IV reports per-design results. Gradient ascent outperforms evolutionary search on all ten designs, achieving up to +113% on aes_core and +96% on the medium design (117K cells), a 1.96× improvement. With β-calibration ablated on aes_core and pci, purely analytical gradients still beat the evolutionary baseline (2,318.3 vs. 1,110.2; 733.4 vs. 481.4), validating the continuous relaxation; β-calibration contributes a further 2–5%. The runtime advantage is decisive. On the medium design, gradient ascent completes in 74 s and achieves a 1.96× higher Pvirus score than evolutionary search given a 1-hour budget. On the large proprietary design (652K cells), gradient ascent completes in 615 s and outperforms evolutionary search, while greedy methods (O(|S|2 )) are entirely infeasible at this scale. VI. D ISCUSSION Why Correlation Matters for Optimization. For power-gradientguided optimization, per-pin correlation is the metric that matters most, more so than aggregate power accuracy. If the model correctly ranks which pins are high-activity versus low-activity, the analytical gradients point in the right direction, and downstream decisions (cell sizing, power virus search) are well-prioritized. A model with perfect correlation but a systematic 2× scale bias would still produce correct gradient directions, and the optimizer would simply adjust its step size. Conversely, a model with low correlation but coincidentally low aggregate error (due to over/under-estimation cancellation) would mislead the optimizer by pointing gradients toward the wrong pins. This is confirmed by the gradient rank experiment: on the medium design (117K cells), the top-500 analytically ranked pins match the top-500 numerically ranked pins exactly (Jaccard = 1.0, Pearson r≈1.0). DiffPower’s hybrid pipeline achieves TR r ≥ 0.937 on nine of ten designs, indicating that pin rankings are highly reliable for optimization. The large design (TR r = 0.84) is the remaining accuracy frontier. Its degradation arises from two interacting factors:

the combinational-boundary treatment cuts deep sequential feedback into wide, irregular logic cones, and within these cones heavy reconvergence violates the temporal-independence assumption faster than per-pin β-calibration can correct. Both are scoping constraints shared by all current differentiable gate-level frameworks [3], [24] and analytical SP methods, not deficiencies of the gradient framework itself. Notably, even on this design SP correlation remains strong (r = 0.969), confirming that the analytical propagation scales correctly. In practice, power optimization is typically applied at the block or partition level (10K–200K cells), a regime where DiffPower achieves TR r ≥ 0.937. Even at the 652K-cell scale, gradient ascent produces power virus scores competitive with evolutionary search, confirming that gradients remain directionally useful. Power Virus: Scalability and Runtime. Gradient ascent outperforms evolutionary search on all evaluated designs (Table IV), even when the evolutionary baseline is given a 1-hour budget with population fitness evaluations parallelized on DiffPower’s own GPU engine. The core advantage is computational: gradient ascent scales as O(T · |pins|) with fixed T =100 steps, completing in 74 s on the medium design (orders of magnitude faster than evolutionary search) while achieving a 1.96× higher Pvirus score. The consistent advantage across design scales confirms that gradient-directed continuous relaxation is consistently more effective than populationbased discrete search for this objective. Future hybrid approaches combining gradient initialization with discrete local refinement could further improve quality on the smallest designs where the gap is generally narrowest. Limitations. As noted above, restricting the analysis to combinational logic between sequential boundaries, the scope shared by prior differentiable gate-level frameworks [3], [24], limits accuracy on deeply sequential designs; sequential power, clock network power, and multi-voltage domain modeling remain open. Infrastructure nets (clock buffers, test-mode signals), though preserved as fixed boundaries with load contributions retained (Section III), are not yet modeled or optimized explicitly; doing so remains a practical prerequisite for full-chip deployment. VII. C ONCLUSION In this paper, we introduced DiffPower, a GPU-accelerated fully differentiable framework that resolves the historical trade-off between speed and accuracy in switching power analysis. By combining a PDK-agnostic bytecode representation with a hybrid propagation pipeline that fuses analytical modeling and bit-packed simulation, DiffPower delivers high-fidelity toggle-rate correlation (median r=0.96) and up to 1,002× speedup over CPU propagation, completing forward and backward passes on a 652K-cell industrial design in under 60 ms. This enables analytical gradient computation on industrial designs at scales exceeding 650K cells. The key insight of this work is that the resulting power gradients translate directly into downstream optimization value. Gradient-weighted cell sizing consistently outperforms local-power heuristics. For power virus generation, gradient ascent outperforms evolutionary search on all ten evaluated designs while reducing runtime from hours to seconds. Key open challenges for future work include the accurate analysis of sequential-heavy designs, explicit modeling of infrastructure nets, and extending the framework to sequential power and multi-voltage domains. The underlying architecture, a levelized GPU graph with bytecode-driven AD, is not specific to combinational switching power and can serve as a foundation for these extensions. ACKNOWLEDGMENT This work was supported in part by NSF Award 2112562 and a gift from Synopsys.

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